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authorAlif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>2025-08-03 18:24:31 -0700
committerTien Fong Chee <tien.fong.chee@intel.com>2025-08-08 16:01:03 +0800
commit60a377db98734e81143df79b54a55afd6ecc4c74 (patch)
tree2b7350b1b31a921d291d930d4c44310384b9cceb /arch/arm/mach-socfpga/spl_agilex.c
parente328332aafe1dc59557d0b144f439509da7042e1 (diff)
arm: socfpga: agilex: Probe DT for firewall setup
Update Agilex SPL code to implement device tree model for firewall registers setup by using DTreg driver to probe from device tree for the firewall settings instead of calling firewall driver function. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/spl_agilex.c')
-rw-r--r--arch/arm/mach-socfpga/spl_agilex.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 91c27a5543d..faba0433838 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -66,7 +66,18 @@ void board_init_f(ulong dummy)
print_reset_info();
cm_print_clock_quick_summary();
- firewall_setup();
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev);
+ if (ret) {
+ printf("System manager firewall configuration failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev);
+ if (ret) {
+ printf("L3 interconnect firewall configuration failed: %d\n", ret);
+ hang();
+ }
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
debug("CCU init failed: %d\n", ret);