arm: socfpga: Convert system manager from struct to defines

Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get system manager base address from DT node instead of
using #define.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

1 files changed, 26 insertions, 16 deletions

diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
index 122828c9ce4..72b10946c61 100644
--- a/arch/arm/mach-socfpga/system_manager_s10.c
+++ b/arch/arm/mach-socfpga/system_manager_s10.c
@@ -10,9 +10,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 /*
  * Configure all the pin muxes
  */
@@ -32,24 +29,33 @@ void populate_sysmgr_fpgaintf_module(void)
 	u32 handoff_val = 0;
 
 	/* Enable the signal for those HPS peripherals that use FPGA. */
-	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NAND_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_NAND;
-	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SDMMC_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
-	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SPIM0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
-	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SPIM1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_SPIM1;
-	writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
+	writel(handoff_val,
+	       socfpga_get_sysmgr_addr() + SYSMGR_S10_FPGAINTF_EN2);
 
 	handoff_val = 0;
-	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC0_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
-	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC1_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
-	if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+	if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC2_USEFPGA) ==
+	    SYSMGR_FPGAINTF_USEFPGA)
 		handoff_val |= SYSMGR_FPGAINTF_EMAC2;
-	writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
+	writel(handoff_val,
+	       socfpga_get_sysmgr_addr() + SYSMGR_S10_FPGAINTF_EN3);
 }
 
 /*
@@ -64,14 +70,16 @@ void populate_sysmgr_pinmux(void)
 	sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
-		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
+		       sys_mgr_table_u32[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_PINSEL0);
 	}
 
 	/* setup the pin ctrl */
 	sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
-		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
+		       sys_mgr_table_u32[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_IOCTRL0);
 	}
 
 	/* setup the fpga use */
@@ -79,13 +87,15 @@ void populate_sysmgr_pinmux(void)
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
 		       sys_mgr_table_u32[i] +
-		       (u8 *)&sysmgr_regs->rgmii0usefpga);
+		       (u8 *)socfpga_get_sysmgr_addr() +
+		       SYSMGR_S10_EMAC0_USEFPGA);
 	}
 
 	/* setup the IO delay */
 	sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
 	for (i = 0; i < len; i = i + 2) {
 		writel(sys_mgr_table_u32[i + 1],
-		       sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
+		       sys_mgr_table_u32[i] +
+		       (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_IODELAY0);
 	}
 }