diff options
author | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
commit | 21e25992c86306b41caafcf85efc47d66f5efa6e (patch) | |
tree | 3c9f1ccb01f1a83f077064b4e4f4e028760f2e39 /arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | |
parent | b4eb57766314062e3dd1ee8e439d2cb2d5dc33d8 (diff) | |
parent | e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7 (diff) |
Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
Diffstat (limited to 'arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h')
-rw-r--r-- | arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 47 |
1 files changed, 37 insertions, 10 deletions
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 240c5c44bcb..ac300768ca0 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -20,7 +20,8 @@ #define DEFAULT_ADDRESS 0xFFFFFFFF #define CMD_SIZE 512 -#define OTP_SIZE 1024 +#define OTP_SIZE_SMC 1024 +#define OTP_SIZE_TA 776 #define PMIC_SIZE 8 enum stm32prog_target { @@ -41,6 +42,7 @@ enum stm32prog_link_t { enum stm32prog_header_t { HEADER_NONE, HEADER_STM32IMAGE, + HEADER_STM32IMAGE_V2, HEADER_FIP, }; @@ -48,11 +50,12 @@ struct image_header_s { enum stm32prog_header_t type; u32 image_checksum; u32 image_length; + u32 length; }; -struct raw_header_s { +struct stm32_header_v1 { u32 magic_number; - u32 image_signature[64 / 4]; + u8 image_signature[64]; u32 image_checksum; u32 header_version; u32 image_length; @@ -63,19 +66,38 @@ struct raw_header_s { u32 version_number; u32 option_flags; u32 ecdsa_algorithm; - u32 ecdsa_public_key[64 / 4]; - u32 padding[83 / 4]; - u32 binary_type; + u8 ecdsa_public_key[64]; + u8 padding[83]; + u8 binary_type; }; -#define BL_HEADER_SIZE sizeof(struct raw_header_s) +struct stm32_header_v2 { + u32 magic_number; + u8 image_signature[64]; + u32 image_checksum; + u32 header_version; + u32 image_length; + u32 image_entry_point; + u32 reserved1; + u32 load_address; + u32 reserved2; + u32 version_number; + u32 extension_flags; + u32 extension_headers_length; + u32 binary_type; + u8 padding[16]; + u32 extension_header_type; + u32 extension_header_length; + u8 extension_padding[376]; +}; /* partition type in flashlayout file */ enum stm32prog_part_type { PART_BINARY, + PART_FIP, PART_SYSTEM, PART_FILESYSTEM, - RAW_IMAGE + RAW_IMAGE, }; /* device information */ @@ -147,6 +169,12 @@ struct stm32prog_data { u32 dtb; u32 initrd; u32 initrd_size; + + u32 script; + + /* OPTEE PTA NVMEM */ + struct udevice *tee; + u32 tee_session; }; extern struct stm32prog_data *stm32prog_data; @@ -166,8 +194,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, int stm32prog_pmic_start(struct stm32prog_data *data); /* generic part*/ -void stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header); +void stm32prog_header_check(uintptr_t raw_header, struct image_header_s *header); int stm32prog_dfu_init(struct stm32prog_data *data); void stm32prog_next_phase(struct stm32prog_data *data); void stm32prog_do_reset(struct stm32prog_data *data); |