diff options
| author | Simon Glass <sjg@chromium.org> | 2021-06-27 17:51:03 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2021-07-15 19:50:09 +0800 |
| commit | 7052968707b2c16da6b9c43aa058435d2932eb82 (patch) | |
| tree | 7590208705559ae124277914e8ef9d3ebcccac2e /arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | |
| parent | 0f5ca1d1f1d399191d6481d1c8853c9ca6fe25ff (diff) | |
x86: Do cache set-up by default when booting from coreboot
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.
If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h')
0 files changed, 0 insertions, 0 deletions