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author | Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> | 2022-08-19 17:01:06 +0800 |
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committer | Tom Rini <trini@konsulko.com> | 2022-09-13 12:08:40 -0400 |
commit | 5150e908f54c3bd0fdd30eefdffaf49c826881ba (patch) | |
tree | 959e98d8fe96e213712cc4c6ddeb0f301e531b63 /arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | |
parent | 456f716f36578bcb86596b73750aa55d5851b4de (diff) |
spi: aspeed: Support AST2400 platform
Although AST2400 is EOL officially, in order to achieve
sustainability and completeness, AST2400 part is added.
For AST2400,
- Five CSs are supported by FMC controller.
- SPI1 controller only supports single CS and there is
no address segment address register. The CE control
register of SPI1 is located at the offset 0x04 and
the 4-byte address mode control bit is bit 13 of
this register.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c')
0 files changed, 0 insertions, 0 deletions