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author | Quentin Schulz <quentin.schulz@cherry.de> | 2025-01-31 11:31:29 +0100 |
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committer | Kever Yang <kever.yang@rock-chips.com> | 2025-05-06 15:59:43 +0800 |
commit | 96f9e112550cd195fcc712ed5092a6f348ca76d8 (patch) | |
tree | 40e7ca5fcf7242f5bd2c78e8c80faf2c7adb7c26 /arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | |
parent | 24c56a160aaf85fbe113b771a56b9a51f913f823 (diff) |
pinctrl: rockchip: fix bank's pin_base computing
The logic in the core reads the nr_pins of the controller and uses it as
the index of the first pin in the bank (pin_base) it currently parses.
It then increments the number of pins in the controller before going to
the next bank.
This works "fine" for controllers where nr_pins isn't defined in their
rockchip_pin_ctrl struct as it defaults to 0. However, when it is
already set, it'll make the index pin of each bank offset by the number
in nr_pins declared in the struct at initialization, and it'll keep
growing while adding banks, which means the total number of pins in the
controller will be misrepresented.
Additionally, U-Boot proper may probe this driver twice (pre-reloc and
true proper) and not reset nr_pins of the controller in-between meaning
the second probe will have an offset of the actual correct nr_pins.
Instead, let's just store locally the number of pins in the controller
and make sure it's reset between probes.
Finally, this stops modifying a const struct which will soon be
triggering a CPU abort at runtime.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c')
0 files changed, 0 insertions, 0 deletions