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authorTom Rini <trini@konsulko.com>2019-05-24 08:13:27 -0400
committerTom Rini <trini@konsulko.com>2019-05-24 08:13:27 -0400
commit866a78dc28411f4c76ba887f439f69f1116d8a6b (patch)
treee9e7f1255f290783c4f748983debbf832495764e /arch/arm/mach-stm32mp/include/mach/ddr.h
parentafe9e1f197e6d0ee4fa59d56639ca56d5f2ed566 (diff)
parent187c41d783371dc3b7ecae45f450b330f5e1bb25 (diff)
Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-boot
- Add various STM32MP1 fixes for serial, env, clk, board, i2c ... - Add STM32MP1 DDR driver update: These update introduce the DDR interactive mode described in: https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode This mode is used by the CubeMX: DDR tuning tool. https://wiki.st.com/stm32mpu/index.php/STM32CubeMX The DDR interactive mode is NOT activated by default because it increase the SPL size and slow down the boot time (200ms wait added).
Diffstat (limited to 'arch/arm/mach-stm32mp/include/mach/ddr.h')
-rw-r--r--arch/arm/mach-stm32mp/include/mach/ddr.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/ddr.h b/arch/arm/mach-stm32mp/include/mach/ddr.h
index 18575842ba9..b8a17cfbddb 100644
--- a/arch/arm/mach-stm32mp/include/mach/ddr.h
+++ b/arch/arm/mach-stm32mp/include/mach/ddr.h
@@ -6,6 +6,13 @@
#ifndef __MACH_STM32MP_DDR_H_
#define __MACH_STM32MP_DDR_H_
-int board_ddr_power_init(void);
+/* DDR power initializations */
+enum ddr_type {
+ STM32MP_DDR3,
+ STM32MP_LPDDR2,
+ STM32MP_LPDDR3,
+};
+
+int board_ddr_power_init(enum ddr_type ddr_type);
#endif