diff options
| author | Tom Rini <trini@konsulko.com> | 2022-06-20 08:09:24 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-20 08:09:24 -0400 |
| commit | 2f7821a9278e710b2e825018303c2942f920a77d (patch) | |
| tree | 8e4d97bcd17960370457134c0770276e5fecc209 /arch/arm/mach-stm32mp/include/mach/stm32.h | |
| parent | a9e90d357bbf539e07c1d971161e027eb335183e (diff) | |
| parent | eae488b77906692627622abc61f5b7160b6eb2a4 (diff) | |
Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
Diffstat (limited to 'arch/arm/mach-stm32mp/include/mach/stm32.h')
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/stm32.h | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 47e88fc3dcd..c70375a723c 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -17,7 +17,9 @@ #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 +#ifdef CONFIG_STM32MP15x #define STM32_DBGMCU_BASE 0x50081000 +#endif #define STM32_FMC2_BASE 0x58002000 #define STM32_DDRCTRL_BASE 0x5A003000 #define STM32_DDRPHYC_BASE 0x5A004000 @@ -26,8 +28,14 @@ #define STM32_STGEN_BASE 0x5C008000 #define STM32_TAMP_BASE 0x5C00A000 +#ifdef CONFIG_STM32MP15x #define STM32_USART1_BASE 0x5C000000 #define STM32_USART2_BASE 0x4000E000 +#endif +#ifdef CONFIG_STM32MP13x +#define STM32_USART1_BASE 0x4c000000 +#define STM32_USART2_BASE 0x4c001000 +#endif #define STM32_USART3_BASE 0x4000F000 #define STM32_UART4_BASE 0x40010000 #define STM32_UART5_BASE 0x40011000 @@ -39,8 +47,10 @@ #define STM32_SDMMC2_BASE 0x58007000 #define STM32_SDMMC3_BASE 0x48004000 +#ifdef CONFIG_STM32MP15x #define STM32_SYSRAM_BASE 0x2FFC0000 #define STM32_SYSRAM_SIZE SZ_256K +#endif #define STM32_DDR_BASE 0xC0000000 #define STM32_DDR_SIZE SZ_1G @@ -98,6 +108,8 @@ enum boot_device { /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) + +#ifdef CONFIG_STM32MP15x #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) @@ -111,13 +123,18 @@ enum boot_device { #define TAMP_COPRO_STATE_CSTOP 3 #define TAMP_COPRO_STATE_STANDBY 4 #define TAMP_COPRO_STATE_CRASH 5 +#endif + +#ifdef CONFIG_STM32MP13x +#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) +#endif #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) -#define TAMP_BOOT_DEBUG_ON BIT(16) enum forced_boot_mode { BOOT_NORMAL = 0x00, @@ -138,11 +155,19 @@ enum forced_boot_mode { #define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) /* BSEC OTP index */ +#ifdef CONFIG_STM32MP15x #define BSEC_OTP_RPN 1 #define BSEC_OTP_SERIAL 13 #define BSEC_OTP_PKG 16 #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 59 +#endif +#ifdef CONFIG_STM32MP13x +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_SERIAL 13 +#define BSEC_OTP_MAC 57 +#define BSEC_OTP_BOARD 60 +#endif #endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ |