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| author | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-05-10 15:28:02 -0400 |
| commit | 21e25992c86306b41caafcf85efc47d66f5efa6e (patch) | |
| tree | 3c9f1ccb01f1a83f077064b4e4f4e028760f2e39 /arch/arm/mach-stm32mp/psci.c | |
| parent | b4eb57766314062e3dd1ee8e439d2cb2d5dc33d8 (diff) | |
| parent | e198d4fe7c34cbb97d7d3cbf31d3a78a5ecc43f7 (diff) | |
Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
Diffstat (limited to 'arch/arm/mach-stm32mp/psci.c')
| -rw-r--r-- | arch/arm/mach-stm32mp/psci.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 86c160987a9..1e69673e88b 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -26,6 +26,7 @@ #define PWR_MPUCR_CSSF BIT(9) /* RCC */ +#define RCC_MSSCKSELR 0x48 #define RCC_DDRITFCR 0xd8 #define RCC_DDRITFCR_DDRC1EN BIT(0) @@ -49,6 +50,10 @@ #define RCC_MP_CIFR 0x418 #define RCC_MP_CIFR_WKUPF BIT(20) +#define RCC_MCUDIVR 0x830 +#define RCC_PLL3CR 0x880 +#define RCC_PLL4CR 0x894 + /* SYSCFG */ #define SYSCFG_CMPCR 0x20 #define SYSCFG_CMPCR_SW_CTRL BIT(2) @@ -690,6 +695,7 @@ static void __secure ddr_sw_self_refresh_exit(void) void __secure psci_system_suspend(u32 __always_unused function_id, u32 ep, u32 context_id) { + u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 saved_pwrctl, reg; /* Disable IO compensation */ @@ -708,6 +714,11 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_PWR_BASE + PWR_MPUCR, PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); + psci_v7_flush_dcache_all(); ddr_sr_mode_ssr(&saved_pwrctl); ddr_sw_self_refresh_in(); @@ -724,6 +735,11 @@ void __secure psci_system_suspend(u32 __always_unused function_id, ddr_sw_self_refresh_exit(); ddr_sr_mode_restore(saved_pwrctl); + writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR); + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); } |