diff options
| author | Tom Rini <trini@konsulko.com> | 2024-04-19 07:28:43 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-04-19 14:25:04 -0600 |
| commit | af04f37a78c7e61597fb9ed6db2c8f8d7f8b0f92 (patch) | |
| tree | 2f724d6d7776f4a79bcc41274035240ed3b0b6a5 /arch/arm/mach-stm32mp/stm32mp1/psci.c | |
| parent | c9e25d8c1d2c844ab76a7b0195f293275dcfdc6e (diff) | |
| parent | b0283b5e3d37daff48b45c3f98d298844603def4 (diff) | |
Merge tag 'u-boot-stm32-20240419' of https://source.denx.de/u-boot/custodians/u-boot-stm
MP1:
_ Add OHCI HCD support for STM32MP15xx DHSOM
_ Report OTP-CLOSED instead of rev.? on closed STM32MP15xx
_ Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
_ Jump to ep on successful resume in PSCI suspend code
_ Add FASTBOOT support for STM32MP13
_ Fix/Rework key and leds management for STM32MP13/15
_ net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support
MP2:
_ Add stm32-fmc-ebi support
_ Add: sdmmc2 support and fix AARCH64 compilation
Diffstat (limited to 'arch/arm/mach-stm32mp/stm32mp1/psci.c')
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp1/psci.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c index 8cdeb0ab3f2..4f2379df45f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/psci.c +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -703,6 +703,8 @@ void __secure psci_system_suspend(u32 __always_unused function_id, { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 gicd_addr = stm32mp_get_gicd_base_address(); + u32 cpu = psci_get_cpu_id(); + u32 sp = (u32)__secure_stack_end - (cpu << ARM_PSCI_STACK_SHIFT); bool iwdg1_wake = false; bool iwdg2_wake = false; bool other_wake = false; @@ -805,4 +807,16 @@ void __secure psci_system_suspend(u32 __always_unused function_id, writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + + /* + * The system has resumed successfully. Rewrite LR register stored + * on stack with 'ep' value, so that on return from this PSCI call, + * the code would jump to that 'ep' resume entry point code path + * instead of the previous 'lr' register content which (e.g. with + * Linux) points to resume failure code path. + * + * See arch/arm/cpu/armv7/psci.S _smc_psci: for the stack layout + * used here, SP-4 is PC, SP-8 is LR, SP-12 is R7, and so on. + */ + writel(ep, sp - 8); } |