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authorTom Rini <trini@konsulko.com>2022-09-26 11:28:14 -0400
committerTom Rini <trini@konsulko.com>2022-09-26 11:28:14 -0400
commit55ccdee3155c6cc30eeee846879d06aba6e3fabe (patch)
tree4cda01be7fa0553410ffc193f4f931910efbbf57 /arch/arm/mach-versal-net/include/mach/sys_proto.h
parentffa2c88bcf8618b6d6fb71f5263beede9a179b20 (diff)
parentf2641f066b53a2bbb933bccffd696a875fd9adf5 (diff)
Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
Diffstat (limited to 'arch/arm/mach-versal-net/include/mach/sys_proto.h')
-rw-r--r--arch/arm/mach-versal-net/include/mach/sys_proto.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h
new file mode 100644
index 00000000000..5bba9030f2d
--- /dev/null
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 - 2022, Xilinx, Inc.
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ */
+
+#include <linux/build_bug.h>
+
+void mem_map_fill(void);
+
+static inline int zynqmp_mmio_write(const u32 address, const u32 mask,
+ const u32 value)
+{
+ BUILD_BUG();
+ return -EINVAL;
+}