Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	arch/arm/include/asm/mach-types.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

5 files changed, 203 insertions, 169 deletions

diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
index 4b566a75ccd..519bfd8b0c2 100644
--- a/arch/i386/cpu/sc520/sc520.c
+++ b/arch/i386/cpu/sc520/sc520.c
@@ -44,24 +44,24 @@ void init_sc520(void)
 	/* Set the UARTxCTL register at it's slower,
 	 * baud clock giving us a 1.8432 MHz reference
 	 */
-	sc520_mmcr->uart1ctl = 0x07;
-	sc520_mmcr->uart2ctl = 0x07;
+	writeb(0x07, &sc520_mmcr->uart1ctl);
+	writeb(0x07, &sc520_mmcr->uart2ctl);
 
 	/* first set the timer pin mapping */
-	sc520_mmcr->clksel = 0x72;	/* no clock frequency selected, use 1.1892MHz */
+	writeb(0x72, &sc520_mmcr->clksel);	/* no clock frequency selected, use 1.1892MHz */
 
 	/* enable PCI bus arbitrer */
-	sc520_mmcr->sysarbctl = 0x02;	/* enable concurrent mode */
+	writeb(0x02, &sc520_mmcr->sysarbctl);	/* enable concurrent mode */
 
-	sc520_mmcr->sysarbmenb = 0x1f;	/* enable external grants */
-	sc520_mmcr->hbctl = 0x04;	/* enable posted-writes */
+	writeb(0x1f, &sc520_mmcr->sysarbmenb);	/* enable external grants */
+	writeb(0x04, &sc520_mmcr->hbctl);	/* enable posted-writes */
 
 	if (CONFIG_SYS_SC520_HIGH_SPEED) {
-		sc520_mmcr->cpuctl = 0x02;	/* set it to 133 MHz and write back */
+		writeb(0x02, &sc520_mmcr->cpuctl);	/* set it to 133 MHz and write back */
 		gd->cpu_clk = 133000000;
 		printf("## CPU Speed set to 133MHz\n");
 	} else {
-		sc520_mmcr->cpuctl = 0x01;	/* set it to 100 MHz and write back */
+		writeb(0x01, &sc520_mmcr->cpuctl);	/* set it to 100 MHz and write back */
 		printf("## CPU Speed set to 100MHz\n");
 		gd->cpu_clk = 100000000;
 	}
@@ -74,7 +74,7 @@ void init_sc520(void)
 	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
-	sc520_mmcr->dbctl = 0x11;
+	writeb(0x11, &sc520_mmcr->dbctl);
 
 	/* turn on the cache and disable write through */
 	asm("movl	%%cr0, %%eax\n"
@@ -88,6 +88,7 @@ unsigned long init_sc520_dram(void)
 
 	u32 dram_present=0;
 	u32 dram_ctrl;
+
 #ifdef CONFIG_SYS_SDRAM_DRCTMCTL
 	/* these memory control registers are set up in the assember part,
 	 * in sc520_asm.S, during 'mem_init'.  If we muck with them here,
@@ -97,7 +98,8 @@ unsigned long init_sc520_dram(void)
 	 * simply dictates it.
 	 */
 #else
-	int val;
+	u8 tmp;
+	u8 val;
 
 	int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
 	int refresh_rate        = CONFIG_SYS_SDRAM_REFRESH_RATE;
@@ -116,9 +118,10 @@ unsigned long init_sc520_dram(void)
 		val = 3;  /* 62.4us */
 	}
 
-	sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4);
+	tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
+	writeb(tmp, &sc520_mmcr->drcctl);
 
-	val = sc520_mmcr->drctmctl & 0xf0;
+	val = readb(&sc520_mmcr->drctmctl) & 0xf0;
 
 	if (cas_precharge_delay==3) {
 		val |= 0x04;   /* 3T */
@@ -133,12 +136,12 @@ unsigned long init_sc520_dram(void)
 	} else {
 		val |= 1;
 	}
-	sc520_mmcr->drctmctl = val;
+	writeb(val, &c520_mmcr->drctmctl);
 #endif
 
 	/* We read-back the configuration of the dram
 	 * controller that the assembly code wrote */
-	dram_ctrl = sc520_mmcr->drcbendadr;
+	dram_ctrl = readl(&sc520_mmcr->drcbendadr);
 
 	bd->bi_dram[0].start = 0;
 	if (dram_ctrl & 0x80) {
@@ -191,7 +194,7 @@ void reset_cpu(ulong addr)
 {
 	printf("Resetting using SC520 MMCR\n");
 	/* Write a '1' to the SYS_RST of the RESCFG MMCR */
-	sc520_mmcr->rescfg = 0x01;
+	writeb(0x01, &sc520_mmcr->rescfg);
 
 	/* NOTREACHED */
 }
diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S
index 2042d9bfcf8..fff56c00b4f 100644
--- a/arch/i386/cpu/sc520/sc520_asm.S
+++ b/arch/i386/cpu/sc520/sc520_asm.S
@@ -25,48 +25,85 @@
  * copyright is included below
  */
 
-/*
- *  =============================================================================
- *
- *   Copyright 1999 Advanced Micro Devices, Inc.
- *
- *  This software is the property of Advanced Micro Devices, Inc  (AMD)  which
- *  specifically grants the user the right to modify, use and distribute this
- *  software provided this COPYRIGHT NOTICE is not removed or altered.  All
- *  other rights are reserved by AMD.
- *
- *  THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
- *  OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
- *  THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
- *  IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
- *  (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
- *  INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY
- *  TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
- *  SUCH DAMAGES.  BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
- *  LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
- *  LIMITATION MAY NOT APPLY TO YOU.
- *
- *  AMD does not assume any responsibility for any errors that may appear in
- *  the Materials nor any responsibility to support or update the Materials.
- *  AMD retains the right to make changes to its test specifications at any
- *  time, without notice.
- *
- *  So that all may benefit from your experience, please report  any  problems
- *  or suggestions about this software back to AMD.  Please include your name,
- *  company,  telephone number,  AMD product requiring support and question or
- *  problem encountered.
- *
- *  Advanced Micro Devices, Inc.         Worldwide support and contact
- *  Embedded Processor Division            information available at:
- *  Systems Engineering                       epd.support@amd.com
- *  5204 E. Ben White Blvd.                          -or-
- *  Austin, TX 78741                http://www.amd.com/html/support/techsup.html
- *  ============================================================================
+/*		TITLE	SIZER - Aspen DRAM Sizing Routine.
+ * =============================================================================
+ *
+ *  Copyright 1999 Advanced Micro Devices, Inc.
+ * You may redistribute this program and/or modify this program under the terms
+ * of the GNU General Public License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ *  This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
+ * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
+ * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
+ * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
+ * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
+ * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGES.  BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
+ * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
+ * LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors that may appear in
+ * the Materials nor any responsibility to support or update the Materials.
+ * AMD retains the right to make changes to its test specifications at any
+ * time, without notice.
+ * ==============================================================================
  */
 
-
-/*******************************************************************************
- *	 AUTHOR      : Buddy Fey - Original.
+/*
+ ******************************************************************************
+ *
+ *  FILE        : sizer.asm - SDRAM DIMM Sizing Algorithm
+ *
+ *
+ *
+ *  FUNCTIONS   : sizemem() - jumped to, not called.  To be executed after
+ *                reset to determine the size of the SDRAM DIMMs. Initializes
+ *		 the memory subsystem.
+ *
+ *
+ *  AUTHOR      : Buddy Fey - Original.
+ *
+ *
+ *  DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
+ *                NOTE: This is a small memory model version
+ *
+ *
+ *  INPUTS      : BP contains return address offset
+ *		 CACHE is assumed to be disabled.
+ *		 The FS segment limit has already been set to big real mode
+ *		 (full 32-bit addressing capability)
+ *
+ *
+ *  OUTPUTS     : None
+ *
+ *
+ *  REG USE     :  ax,bx,cx,dx,di,si,bp, fs
+ *
+ *
+ *  REVISION    : See PVCS info below
+ *
+ *
+ *  TEST PLAN CROSS REFERENCE:
+ *
+ *
+ * $Workfile: $
+ * $Revision: 1.2 $
+ * $Date: 1999/09/22 12:49:33 $
+ * $Author: chipf $
+ * $Log: sizer.asm $
+ * Revision 1.2  1999/09/22 12:49:33  chipf
+ * Add legal header
+ *
  *******************************************************************************
  */
 
@@ -463,7 +500,7 @@ emptybank:
 	/* just have your hardware desinger _GIVE_ you what you need here! */
 	movl    $DRCTMCTL, %edi
 	movb    $CONFIG_SYS_SDRAM_DRCTMCTL,%al
-	movb    (%edi), %al
+	movb    %al, (%edi)
 #else
 #if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
 	/* set the CAS latency now since it is hard to do
@@ -498,48 +535,21 @@ bad_ram:
 
 dram_done:
 
-	/* readback DRCBENDADR and return the number
-	 * of available ram bytes in %eax */
-
-	movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
-
-	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x80000000, %ecx
-	jz	bank2
-	andl	$0x7f000000, %eax
-	shrl	$2, %eax
-	movl	%eax, %ebx
-
-bank2:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x00800000, %ecx
-	jz	bank1
-	andl	$0x007f0000, %eax
-	shll	$6, %eax
-	movl	%eax, %ebx
-
-bank1:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x00008000, %ecx
-	jz	bank0
-	andl	$0x00007f00, %eax
-	shll	$14, %eax
-	movl	%eax, %ebx
-
-bank0:	movl	(%edi), %eax
-	movl	%eax, %ecx
-	andl	$0x00000080, %ecx
-	jz	done
-	andl	$0x0000007f, %eax
-	shll	$22, %eax
-	movl	%eax, %ebx
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+	/*
+	 * We are in the middle of an existing 'call' - Need to store the
+	 * existing return address before making another 'call'
+	 */
+	movl	%ebp, %ebx
 
+	/* Get the memory size */
+	movl	$init_ecc, %ebp
+	jmpl	get_mem_size
 
-done:
-	movl	%ebx, %eax
+init_ecc:
+	/* Restore the orignal return address */
+	movl	%ebx, %ebp
 
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
 	/* A nominal memory test: just a byte at each address line */
 	movl    %eax, %ecx
 	shrl    $0x1, %ecx
@@ -576,6 +586,50 @@ set_ecc:
 	mov	$0x05, %al
 	movb    %al, (%edi)
 #endif
+
 out:
+	jmp	*%ebp
+
+/*
+ * Read and decode the sc520 DRCBENDADR MMCR and return the number of
+ * available ram bytes in %eax
+ */
+.globl get_mem_size
+get_mem_size:
+	movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
+
+bank0:	movl	(%edi), %eax
+	movl	%eax, %ecx
+	andl	$0x00000080, %ecx
+	jz	bank1
+	andl	$0x0000007f, %eax
+	shll	$22, %eax
+	movl	%eax, %ebx
+
+bank1:	movl	(%edi), %eax
+	movl	%eax, %ecx
+	andl	$0x00008000, %ecx
+	jz	bank2
+	andl	$0x00007f00, %eax
+	shll	$14, %eax
+	movl	%eax, %ebx
+
+bank2:	movl	(%edi), %eax
+	movl	%eax, %ecx
+	andl	$0x00800000, %ecx
+	jz	bank3
+	andl	$0x007f0000, %eax
+	shll	$6, %eax
+	movl	%eax, %ebx
+
+bank3:	movl	(%edi), %eax
+	movl	%eax, %ecx
+	andl	$0x80000000, %ecx
+	jz	done
+	andl	$0x7f000000, %eax
+	shrl	$2, %eax
+	movl	%eax, %ebx
+
+done:
 	movl	%ebx, %eax
 	jmp	*%ebp
diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c
index f446c6d5927..b91773435e9 100644
--- a/arch/i386/cpu/sc520/sc520_pci.c
+++ b/arch/i386/cpu/sc520/sc520_pci.c
@@ -25,7 +25,9 @@
 
 #include <common.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
+#include <asm/ic/pci.h>
 #include <asm/ic/sc520.h>
 
 static struct {
@@ -63,6 +65,8 @@ int sc520_pci_ints[15] = {
 int pci_sc520_set_irq(int pci_pin, int irq)
 {
 	int i;
+	u8 tmpb;
+	u16 tmpw;
 
 # if 1
 	printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
@@ -80,31 +84,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
 
 	/* PCI interrupt mapping (A through D)*/
 	for (i=0; i<=3 ;i++) {
-		if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority)
-			sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED;
+		if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
+			writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
 	}
 
 	/* GP IRQ interrupt mapping */
 	for (i=0; i<=10 ;i++) {
-		if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority)
-			sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED;
+		if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
+			writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
 	}
 
 	/* Set the trigger to level */
-	sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] =
-		sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit;
+	tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
+	tmpb |= sc520_irq[irq].level_bit;
+	writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
 
 
 	if (pci_pin < 4) {
 		/* PCI INTA-INTD */
 		/* route the interrupt */
-		sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority;
+		writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
 	} else {
 		/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
-		sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority;
+		writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
 
 		/* also set the polarity in this case */
-		sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4));
+		tmpw = readw(&sc520_mmcr->intpinpol);
+		tmpw |= (1 << (pci_pin-4));
+		writew(tmpw, &sc520_mmcr->intpinpol);
 	}
 
 	/* register the pin */
@@ -118,43 +125,7 @@ void pci_sc520_init(struct pci_controller *hose)
 {
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
-
-	/* System memory space */
-	pci_set_region(hose->regions + 0,
-		       SC520_PCI_MEMORY_BUS,
-		       SC520_PCI_MEMORY_PHYS,
-		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 1,
-		       SC520_PCI_MEM_BUS,
-		       SC520_PCI_MEM_PHYS,
-		       SC520_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* ISA/PCI memory space */
-	pci_set_region(hose->regions + 2,
-		       SC520_ISA_MEM_BUS,
-		       SC520_ISA_MEM_PHYS,
-		       SC520_ISA_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region(hose->regions + 3,
-		       SC520_PCI_IO_BUS,
-		       SC520_PCI_IO_PHYS,
-		       SC520_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	/* ISA/PCI I/O space */
-	pci_set_region(hose->regions + 4,
-		       SC520_ISA_IO_BUS,
-		       SC520_ISA_IO_PHYS,
-		       SC520_ISA_IO_SIZE,
-		       PCI_REGION_IO);
-
-	hose->region_count = 5;
+	hose->region_count = pci_set_regions(hose);
 
 	pci_setup_type1(hose,
 			SC520_REG_ADDR,
diff --git a/arch/i386/cpu/sc520/sc520_ssi.c b/arch/i386/cpu/sc520/sc520_ssi.c
index 8dbe17aa60e..6e5e3463033 100644
--- a/arch/i386/cpu/sc520/sc520_ssi.c
+++ b/arch/i386/cpu/sc520/sc520_ssi.c
@@ -24,6 +24,7 @@
 /* stuff specific for the sc520, but independent of implementation */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/ic/ssi.h>
 #include <asm/ic/sc520.h>
 
@@ -61,34 +62,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 		temp |= PHS_INV_ENB;
 	}
 
-	sc520_mmcr->ssictl = temp;
+	writeb(temp, &sc520_mmcr->ssictl);
 
 	return 0;
 }
 
 u8 ssi_txrx_byte(u8 data)
 {
-	sc520_mmcr->ssixmit = data;
-	while (sc520_mmcr->ssista & SSISTA_BSY);
-	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV;
-	while (sc520_mmcr->ssista & SSISTA_BSY);
+	writeb(data, &sc520_mmcr->ssixmit);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
 
-	return sc520_mmcr->ssircv;
+	return readb(&sc520_mmcr->ssircv);
 }
 
 
 void ssi_tx_byte(u8 data)
 {
-	sc520_mmcr->ssixmit = data;
-	while (sc520_mmcr->ssista & SSISTA_BSY);
-	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT;
+	writeb(data, &sc520_mmcr->ssixmit);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
 }
 
 u8 ssi_rx_byte(void)
 {
-	while (sc520_mmcr->ssista & SSISTA_BSY);
-	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV;
-	while (sc520_mmcr->ssista & SSISTA_BSY);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
+	writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
+	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
 
-	return sc520_mmcr->ssircv;
+	return readb(&sc520_mmcr->ssircv);
 }
diff --git a/arch/i386/cpu/sc520/sc520_timer.c b/arch/i386/cpu/sc520/sc520_timer.c
index 93b5b555c30..d5617e91f6e 100644
--- a/arch/i386/cpu/sc520/sc520_timer.c
+++ b/arch/i386/cpu/sc520/sc520_timer.c
@@ -24,13 +24,14 @@
 /* stuff specific for the sc520, but independent of implementation */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/interrupt.h>
 #include <asm/ic/sc520.h>
 
 void sc520_timer_isr(void)
 {
 	/* Ack the GP Timer Interrupt */
-	sc520_mmcr->gptmrsta = 0x02;
+	writeb(0x02, &sc520_mmcr->gptmrsta);
 }
 
 int timer_init(void)
@@ -42,43 +43,47 @@ int timer_init(void)
 	irq_install_handler (0, timer_isr, NULL);
 
 	/* Map GP Timer 1 to Master PIC IR0  */
-	sc520_mmcr->gp_tmr_int_map[1] = 0x01;
+	writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
 
 	/* Disable GP Timers 1 & 2 - Allow configuration writes */
-	sc520_mmcr->gptmr1ctl = 0x4000;
-	sc520_mmcr->gptmr2ctl = 0x4000;
+	writew(0x4000, &sc520_mmcr->gptmr1ctl);
+	writew(0x4000, &sc520_mmcr->gptmr2ctl);
 
 	/* Reset GP Timers 1 & 2 */
-	sc520_mmcr->gptmr1cnt = 0x0000;
-	sc520_mmcr->gptmr2cnt = 0x0000;
+	writew(0x0000, &sc520_mmcr->gptmr1cnt);
+	writew(0x0000, &sc520_mmcr->gptmr2cnt);
 
 	/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
-	sc520_mmcr->gptmr2maxcmpa = 83;
-	sc520_mmcr->gptmr2ctl = 0xc001;
+	writew(83, &sc520_mmcr->gptmr2maxcmpa);
+	writew(0xc001, &sc520_mmcr->gptmr2ctl);
 
 	/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
-	sc520_mmcr->gptmr1maxcmpa = 100;
-	sc520_mmcr->gptmr1ctl = 0xe009;
+	writew(100, &sc520_mmcr->gptmr1maxcmpa);
+	writew(0xe009, &sc520_mmcr->gptmr1ctl);
 
 	unmask_irq (0);
 
 	/* Clear the GP Timer 1 status register to get the show rolling*/
-	sc520_mmcr->gptmrsta = 0x02;
+	writeb(0x02, &sc520_mmcr->gptmrsta);
 
 	return 0;
 }
 
+/* Allow boards to override udelay implementation */
 void __udelay(unsigned long usec)
+	__attribute__((weak, alias("sc520_udelay")));
+
+void sc520_udelay(unsigned long usec)
 {
 	int m = 0;
 	long u;
 	long temp;
 
-	temp = sc520_mmcr->swtmrmilli;
-	temp = sc520_mmcr->swtmrmicro;
+	temp = readw(&sc520_mmcr->swtmrmilli);
+	temp = readw(&sc520_mmcr->swtmrmicro);
 
 	do {
-		m += sc520_mmcr->swtmrmilli;
-		u = sc520_mmcr->swtmrmicro + (m * 1000);
+		m += readw(&sc520_mmcr->swtmrmilli);
+		u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
 	} while (u < usec);
 }