summaryrefslogtreecommitdiff
path: root/arch/mips/lib/cache_init.S
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2024-03-19 09:10:30 -0400
committerTom Rini <trini@konsulko.com>2024-03-19 09:10:30 -0400
commitf048104999db28d49362201eaebfc91adb14f47c (patch)
treed8a909e13b846bb4a443283a3d948a39bb835995 /arch/mips/lib/cache_init.S
parentb145877c22b391a4872c875145a8f86f6ffebaba (diff)
parent386fca68960994ece0d9da8a69a14495b5f1aedf (diff)
Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
- A new driver in the misc to register setting from device tree. This also provides user a clean interface and all register settings are centralized in one place, device tree. - Enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Build-tested on SoC64 boards, boot tested on some of them.
Diffstat (limited to 'arch/mips/lib/cache_init.S')
-rw-r--r--arch/mips/lib/cache_init.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 602741c65dc..d64209d76a9 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -431,9 +431,9 @@ LEAF(change_k0_cca)
#else
xor a0, a0, t0
andi a0, a0, CONF_CM_CMASK
- xor a0, a0, t0
+ xor t0, a0, t0
#endif
- mtc0 a0, CP0_CONFIG
+ mtc0 t0, CP0_CONFIG
jr.hb ra
END(change_k0_cca)