diff options
| author | Tom Rini <trini@konsulko.com> | 2018-12-21 13:36:51 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-21 13:36:51 -0500 |
| commit | fd0135e3c54c391b6143f85440e30d576a9a83fe (patch) | |
| tree | 500ea3c4490f65e30c20e73e571f7982cd6f8c82 /arch/mips/mach-mscc/include/mach/common.h | |
| parent | 328e3f8a706931e1a8f76adfdc015ad76cbeb83c (diff) | |
| parent | 25c7de2255128743fcbe436b6f3b17a70d0cdd82 (diff) | |
Merge tag 'mips-updates-for-2019.11' of git://git.denx.de/u-boot-mips
- mips: fix some DTC warnings
- bmips: bcm6348: add DMA driver
- bmips: bcm5348: add ethernet driver
- bmips: bcm6368: add ethernet driver
- mips: mt76xx: fix DMA problems, disable CONFIG_OF_EMBED
- mips: mscc: add support for Microsemi Ocelot and Luton SoCs
- mips: mscc: add support for Ocelot and Luton evaluation boards
- mips: jz47xx: add basic support for Ingenic JZ4780 SoC
- mips: jz47xx: add support for Imgtec Creator CI20 board
Diffstat (limited to 'arch/mips/mach-mscc/include/mach/common.h')
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/common.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/include/mach/common.h b/arch/mips/mach-mscc/include/mach/common.h new file mode 100644 index 00000000000..931ecd7985e --- /dev/null +++ b/arch/mips/mach-mscc/include/mach/common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#ifndef __ASM_MACH_COMMON_H +#define __ASM_MACH_COMMON_H + +#if defined(CONFIG_SOC_OCELOT) +#include <mach/ocelot/ocelot.h> +#include <mach/ocelot/ocelot_devcpu_gcb.h> +#include <mach/ocelot/ocelot_icpu_cfg.h> +#elif defined(CONFIG_SOC_LUTON) +#include <mach/luton/luton.h> +#include <mach/luton/luton_devcpu_gcb.h> +#include <mach/luton/luton_icpu_cfg.h> +#else +#error Unsupported platform +#endif + +#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ +#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ +#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ +#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ + +#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ + +#endif /* __ASM_MACH_COMMON_H */ |