MSCC: Add support for Serval SoC family.

As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

1 files changed, 24 insertions, 1 deletions

diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
index 37402259a4f..a555fc9d9a9 100644
--- a/arch/mips/mach-mscc/reset.c
+++ b/arch/mips/mach-mscc/reset.c
@@ -27,7 +27,30 @@ void _machine_restart(void)
 	       ICPU_RESET_CORE_RST_CPU_ONLY |
 	       ICPU_RESET_CORE_RST_FORCE,
 	       BASE_CFG + ICPU_RESET);
-#else
+#elif defined(CONFIG_SOC_SERVAL)
+	register unsigned long i;
+
+	/* Prevent VCore-III from being reset with a global reset */
+	writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+
+	/* Do global reset */
+	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+	for (i = 0; i < 1000; i++)
+		;
+
+	/* Power down DDR for clean DDR re-training */
+	writel(readl(BASE_CFG + ICPU_MEMCTRL_CTRL) |
+	       ICPU_MEMCTRL_CTRL_PWR_DOWN,
+	       BASE_CFG + ICPU_MEMCTRL_CTRL);
+
+	while (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT) &
+		 ICPU_MEMCTRL_STAT_PWR_DOWN_ACK))
+		;
+
+	/* Reset VCore-III, only. */
+	writel(ICPU_RESET_CORE_RST_FORCE, BASE_CFG + ICPU_RESET);
+#else		/* Luton || Ocelot */
 	register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
 	(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);