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authorTom Rini <trini@konsulko.com>2020-04-27 17:50:35 -0400
committerTom Rini <trini@konsulko.com>2020-04-27 17:50:35 -0400
commit9b20a794a71151a3a690242b5161b4ca5effd3e7 (patch)
tree6b212ab26b722b8fc7e92218e1eafa22073e96f2 /arch/mips/mach-mtmips/cpu.c
parent37b02289029853033fd662cd4b010336cfb282ad (diff)
parent3fd023143237a5271a21ccec4b94440df257a5a7 (diff)
Merge tag 'mips-pull-2020-04-27' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips
- brcmnand: fix missing code path from Linux driver - bmips: fix build error when disabling USB - mips: add option to restore original exception vector base - mips: fix off-by-one error when clearing gd_data - mips: minor fixes for compatibility with generic SPL framework - spl: refactor legacy image loading - spl: add LZMA decompression support for legacy images - Makefile: add target to build LZMA compressed U-Boot images - mtmips: refactor and rewrite low-level init code - mtmips: add and enable SPL support with LZMA - mtmips: add support for MT7628 reference board - mtmips: add support for VoCore/VoCore2 board
Diffstat (limited to 'arch/mips/mach-mtmips/cpu.c')
-rw-r--r--arch/mips/mach-mtmips/cpu.c58
1 files changed, 3 insertions, 55 deletions
diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c
index 8976ef57c70..459a9673ebe 100644
--- a/arch/mips/mach-mtmips/cpu.c
+++ b/arch/mips/mach-mtmips/cpu.c
@@ -4,69 +4,17 @@
*/
#include <common.h>
-#include <dm.h>
-#include <init.h>
#include <malloc.h>
-#include <ram.h>
-#include <wdt.h>
-#include <asm/io.h>
#include <linux/io.h>
#include <linux/sizes.h>
-#include "mt76xx.h"
-#define STR_LEN 6
-
-#ifdef CONFIG_BOOT_ROM
-int mach_cpu_init(void)
-{
- ddr_calibrate();
-
- return 0;
-}
-#endif
+DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
-
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
- "PLL (4-Byte SPI Addr)",
- "XTAL (3-Byte SPI Addr)",
- "XTAL (4-Byte SPI Addr)" };
- const void *blob = gd->fdt_blob;
- void __iomem *sysc_base;
- char buf[STR_LEN + 1];
- fdt_addr_t base;
- fdt_size_t size;
- char *str;
- int node;
- u32 val;
-
- /* Get system controller base address */
- node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
- if (node < 0)
- return -FDT_ERR_NOTFOUND;
-
- base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
- 0, &size, true);
- if (base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- sysc_base = ioremap_nocache(base, size);
-
- str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
- snprintf(buf, STR_LEN + 1, "%s", str);
- val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
- printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
- (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
-
- val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
- printf("Boot from %s\n", boot_str[val]);
+#endif
return 0;
}