Merge tag 'for-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

mpc83xx, keymile boards: enable DM_ETH and add DTS
  - mpc83xx: remove unneeded extern declaration in cpu_init
  - powerpc, qe: fix codingstyle issues for drivers/qe
  - powerpc, qe: add DTS support for parallel I/O ports
  - net, qe: add DM support for QE UEC ethernet
  - add DTS for all mpc83xx based boards from keymile
    mainly they are not mainlined to linux.
  - add u-boot specific dtsi
  - add stdout-path
  - add missing ucc4 par_io definitions, which were
    in board code, but not in linux DTS
  - remove not used ethernet nodes

1 files changed, 67 insertions, 31 deletions

diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c
index 88aa6895511..52360703a7d 100644
--- a/arch/powerpc/cpu/mpc83xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc83xx/qe_io.c
@@ -12,57 +12,93 @@
 #include <asm/immap_83xx.h>
 
 #define	NUM_OF_PINS	32
-void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+
+/** qe_cfg_iopin configure one io pin setting
+ *
+ * @par_io:	pointer to parallel I/O base
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
+			 int open_drain, int assign)
 {
-	u32			pin_2bit_mask;
-	u32			pin_2bit_dir;
-	u32			pin_2bit_assign;
-	u32			pin_1bit_mask;
-	u32			tmp_val;
-	volatile immap_t	*im = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile qepio83xx_t	*par_io = (volatile qepio83xx_t *)&im->qepio;
+	u32	dbit_mask;
+	u32	dbit_dir;
+	u32	dbit_asgn;
+	u32	bit_mask;
+	u32	tmp_val;
+	int	offset;
+
+	offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
 
 	/* Calculate pin location and 2bit mask and dir */
-	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
-	pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+	dbit_mask = (u32)(0x3 << offset);
+	dbit_dir = (u32)(dir << offset);
 
 	/* Setup the direction */
-	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
 		in_be32(&par_io->ioport[port].dir2) :
 		in_be32(&par_io->ioport[port].dir1);
 
-	if (pin > (NUM_OF_PINS/2) -1) {
-		out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
 	} else {
-		out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
+		out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
 	}
 
 	/* Calculate pin location for 1bit mask */
-	pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+	bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
 
 	/* Setup the open drain */
 	tmp_val = in_be32(&par_io->ioport[port].podr);
-	if (open_drain) {
-		out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
-	} else {
-		out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
-	}
+	if (open_drain)
+		out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
+	else
+		out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
 
 	/* Setup the assignment */
-	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
-		in_be32(&par_io->ioport[port].ppar2):
+	tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+		in_be32(&par_io->ioport[port].ppar2) :
 		in_be32(&par_io->ioport[port].ppar1);
-	pin_2bit_assign = (u32)(assign
-				<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+	dbit_asgn = (u32)(assign << offset);
 
 	/* Clear and set 2 bits mask */
-	if (pin > (NUM_OF_PINS/2) - 1) {
-		out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
+	if (pin > (NUM_OF_PINS / 2) - 1) {
+		out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
 	} else {
-		out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
-		out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
 	}
 }
+
+#if !defined(CONFIG_PINCTRL)
+/** qe_config_iopin configure one io pin setting
+ *
+ * @port:	io pin port
+ * @pin:	io pin number which get configured
+ * @dir:	direction of io pin 2 bits valid
+ *		00 = pin disabled
+ *		01 = output
+ *		10 = input
+ *		11 = pin is I/O
+ * @open_drain:	is pin open drain
+ * @assign:	pin assignment registers select the function of the pin
+ */
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+	immap_t        *im = (immap_t *)CONFIG_SYS_IMMR;
+	qepio83xx_t    *par_io = (qepio83xx_t *)&im->qepio;
+
+	qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
+}
+#endif