diff options
| author | Darwin Dingel <darwin.dingel@alliedtelesis.co.nz> | 2016-10-25 09:48:01 +1300 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-01-24 13:28:02 -0800 |
| commit | 06ad970b53a3d6aa122685e6142a04908434a8ef (patch) | |
| tree | 421d254147fd51429b5d09eead885b9d87d7a526 /arch/powerpc/cpu/mpc85xx/cpu_init.c | |
| parent | 0c9e85f67cd86d2d7a3424ea3ebff0e6db7a3915 (diff) | |
powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907
Core hang occurs when using L1 stashes. Workaround is to disable L1
stashes so software uses L2 cache for stashes instead.
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz>
Cc: York Sun <york.sun@nxp.com>
[York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 822844dfa9f..f5bf67c9903 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -777,6 +777,13 @@ int cpu_init_r(void) sync(); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); + sync(); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 /* * A-005812 workaround sets bit 32 of SPR 976 for SoCs running |