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| author | Tom Rini <trini@konsulko.com> | 2017-01-25 17:09:01 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-01-25 17:38:45 -0500 |
| commit | 79a34b71c943a80af5c6d9a2af736fbb37dcc14c (patch) | |
| tree | c903d3136106e2a566c33eb1366f110220f4c366 /arch/powerpc/cpu/mpc85xx/cpu_init.c | |
| parent | a8523a808fd05e4b1c1df63bc40744dd3fd318f4 (diff) | |
| parent | 76866600f544f00928ee9b5b2799a091ea9b80a7 (diff) | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 822844dfa9f..f5bf67c9903 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -777,6 +777,13 @@ int cpu_init_r(void) sync(); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); + sync(); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 /* * A-005812 workaround sets bit 32 of SPR 976 for SoCs running |