diff options
| author | York Sun <yorksun@freescale.com> | 2013-06-25 11:37:49 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:40 -0700 |
| commit | d217a9ad01ee6557a0c47cfc745eef6890507bbb (patch) | |
| tree | 7905c863e594930b7115b2e6d78a821f6205c79a /arch/powerpc/cpu/mpc85xx/cpu_init.c | |
| parent | c63e137014cf148bc1d234128941dccee3d519ae (diff) | |
powerpc/mpc85xx: Workaround for A-005812
Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 1774462a420..48b38263fde 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -399,6 +399,14 @@ int cpu_init_r(void) sync(); } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005812 + /* + * A-005812 workaround sets bit 32 of SPR 976 for SoCs running + * in write shadow mode. Checking DCWS before setting SPR 976. + */ + if (mfspr(L1CSR2) & L1CSR2_DCWS) + mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); +#endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) spin = getenv("spin_table_compat"); |