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authorTom Rini <trini@konsulko.com>2021-07-07 22:50:41 -0400
committerTom Rini <trini@konsulko.com>2021-07-07 22:50:41 -0400
commitbfb5bfa3c58adc2ef5dbd1bb95b79b31e0dc221c (patch)
tree21753c7f94144a286584c1f631ad9bde89a1a438 /arch/powerpc/cpu/mpc85xx/pci.c
parent7e58a3a148fb94e9ce09fb48d0ddd75c20ee7df9 (diff)
parent123dc510c6e79f0c94718e2e6b5e4074754aa629 (diff)
Merge branch '2021-07-07-remove-non-migrated-platforms'
- Remove a large number of platforms that did not migrate to DM_PCI or DM_USB by 2 years past the migration deadline and do not have a migration imminent.
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/pci.c')
-rw-r--r--arch/powerpc/cpu/mpc85xx/pci.c23
1 files changed, 0 insertions, 23 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
index 9a6fc13b73f..b7835c0fee5 100644
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ b/arch/powerpc/cpu/mpc85xx/pci.c
@@ -120,29 +120,6 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
pci_register_hose(hose);
-#if defined(CONFIG_TARGET_MPC8555CDS) || defined(CONFIG_TARGET_MPC8541CDS)
- /*
- * This is a SW workaround for an apparent HW problem
- * in the PCI controller on the MPC85555/41 CDS boards.
- * The first config cycle must be to a valid, known
- * device on the PCI bus in order to trick the PCI
- * controller state machine into a known valid state.
- * Without this, the first config cycle has the chance
- * of hanging the controller permanently, just leaving
- * it in a semi-working state, or leaving it working.
- *
- * Pick on the Tundra, Device 17, to get it right.
- */
- {
- u8 header_type;
-
- pci_hose_read_config_byte(hose,
- PCI_BDF(0,BRIDGE_ID,0),
- PCI_HEADER_TYPE,
- &header_type);
- }
-#endif
-
hose->last_busno = pci_hose_scan(hose);
#ifdef CONFIG_MPC85XX_PCI2