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authorWolfgang Denk <wd@denx.de>2010-05-17 23:11:21 +0200
committerWolfgang Denk <wd@denx.de>2010-05-17 23:11:21 +0200
commit1a1e6bf12b3155f47d2661793ceee3daded0d937 (patch)
tree9e1b80ccd824be1c6884a0af31a76c79bf4c7c54 /arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
parenta2a0a7171303de5d8ce099344efde2e29ee36eb0 (diff)
parentbcb6c2bb84705bfd73eed5c9a31e9ff24833ee8c (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index d9d0fa70eeb..dcb37cea1f9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh)
* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
* Not certain if any good value exists for CL=2
*/
- /* CL2 CL3 CL4 CL5 CL6 */
-unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 };
+ /* CL2 CL3 CL4 CL5 CL6 CL7*/
+unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
unsigned int
compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)