diff options
| author | Tom Rini <trini@ti.com> | 2012-09-25 12:23:55 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-09-25 12:23:55 -0700 |
| commit | 5675b509165b67465a20e5cf71e07f40b449ef0c (patch) | |
| tree | 9886f3e8fa8734ec9f8d9cb484fcaa87ff70203f /arch/powerpc/include/asm/fsl_ddr_sdram.h | |
| parent | ee1f4caaa2a3f79d692155eec8a4c7289d60e106 (diff) | |
| parent | d69dba367aed051663d0ee1ece013c8232bfa9f5 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/include/asm/fsl_ddr_sdram.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 93639ba8516..e271342f089 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -76,6 +76,13 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_PAGE_INTERLEAVING 0x1 #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA +#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC +#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD +/* placeholder for 4-way interleaving */ +#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A +#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C +#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ @@ -88,6 +95,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 #define SDRAM_CFG_32_BE 0x00080000 #define SDRAM_CFG_16_BE 0x00100000 #define SDRAM_CFG_8_BE 0x00040000 |