diff options
| author | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
| commit | cebdfc22da6eb81793b616e855bc4d6d89c1c7a6 (patch) | |
| tree | 44eaafcbe4866712d361304882e7d56ca0ef1682 /arch/powerpc/include/asm/fsl_pci.h | |
| parent | 62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9 (diff) | |
| parent | fe33066d246462551f385f204690a11018336ac8 (diff) | |
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_pci.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_pci.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 06f9bfb8ac7..809ab1d4187 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCI##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ } #define SET_STD_PCIE_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ } #define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR) #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR) #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) |