diff options
| author | Tom Rini <trini@konsulko.com> | 2020-04-23 08:24:47 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-23 08:24:47 -0400 |
| commit | a5f9b8a8b592400a01771ad2dac76cba69c914f3 (patch) | |
| tree | 23e1c8542fd35083260a97efb0d92b3485889aa1 /arch/riscv/cpu/ax25/cache.c | |
| parent | caad316b3165615f1a4848901811a4a084444c9d (diff) | |
| parent | 177c53fe6c64d8656f5a647116a97047202c5455 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Adds few DT related fixes required for Linux EFI stub to work on
RISC-V.
- Makes SBI v0.2 the default SBI version to work with OpenSBI v0.7.
- Revert "riscv: qemu: clear kernel-start/-end in device tree as
workaround for BBL"
- Remove unnecessary CONFIG_IS_ENABLED().
Diffstat (limited to 'arch/riscv/cpu/ax25/cache.c')
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 9f424198b4a..9df629d23ce 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -12,7 +12,7 @@ #include <asm/csr.h> #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) /* mcctlcommand */ #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc @@ -47,7 +47,7 @@ void flush_dcache_all(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); #endif #endif @@ -68,7 +68,7 @@ void icache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x1\n\t" @@ -83,7 +83,7 @@ void icache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "fence.i\n\t" "csrr t1, mcache_ctl\n\t" @@ -99,7 +99,7 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" @@ -117,7 +117,7 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -137,7 +137,7 @@ int icache_status(void) int ret = 0; #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x01\n\t" @@ -156,7 +156,7 @@ int dcache_status(void) int ret = 0; #ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE) +#if CONFIG_IS_ENABLED(RISCV_MMODE) asm volatile ( "csrr t1, mcache_ctl\n\t" "andi %0, t1, 0x02\n\t" |