diff options
author | Tom Rini <trini@konsulko.com> | 2020-09-30 09:21:43 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2020-09-30 09:21:43 -0400 |
commit | 01114adfc1e0bf3cf5e2f3da858bb2c8e9810c1c (patch) | |
tree | 64ab9c9d1c2a5f3cc96b4c0fef1990cb73c1b356 /arch/riscv/cpu/cpu.c | |
parent | 527fad0b2484bf1dd4c443c4c8f4384aa256938f (diff) | |
parent | 924de3216e9efdf1cdc71b8632099213aac03f2c (diff) |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next
- Disable CMD_IRQ for RISC-V.
- Update sipeed/maix doc
- Obtain reg of SiFive RAM via dev_read_addr_index() instead of regmap API.
- Cleans up RISC-V timer drivers and converts them to DM.
- Correctly handle IPIs already pending upon prior stage bootloader (on the K210)
Diffstat (limited to 'arch/riscv/cpu/cpu.c')
-rw-r--r-- | arch/riscv/cpu/cpu.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bfa2d4a4269..85592f5bee2 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -72,6 +72,17 @@ static int riscv_cpu_probe(void) return 0; } +/* + * This is called on secondary harts just after the IPI is init'd. Currently + * there's nothing to do, since we just need to clear any existing IPIs, and + * that is handled by the sending of an ipi itself. + */ +#if CONFIG_IS_ENABLED(SMP) +static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) +{ +} +#endif + int arch_cpu_init_dm(void) { int ret; @@ -111,6 +122,15 @@ int arch_cpu_init_dm(void) ret = riscv_init_ipi(); if (ret) return ret; + + /* + * Clear all pending IPIs on secondary harts. We don't do anything on + * the boot hart, since we never send an IPI to ourselves, and no + * interrupts are enabled + */ + ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0); + if (ret) + return ret; #endif return 0; |