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| author | Tom Rini <trini@konsulko.com> | 2025-05-21 08:59:10 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-05-21 09:00:21 -0600 |
| commit | 8f85a7345ed5df70a155f0630da72970eb01d87a (patch) | |
| tree | 10acf511e4f955f5874d9e64331c841609b4804a /arch/riscv/cpu/cpu.c | |
| parent | 0a87352281ade2b822ce0360e1f105f6e43a96e1 (diff) | |
| parent | ff6e20c32ff33c6963f7d0a79a0914681461f4fa (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26259
- Initial SPL support for T-Head TH1520 SoC
- Improve usability of TH1520 with mainline SPL
- Support building RV32 & RV64 images
- riscv: Improve jh7110 support
Diffstat (limited to 'arch/riscv/cpu/cpu.c')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 5b31da64cbd..15c4e14599d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -18,6 +18,7 @@ #include <asm/hwcap.h> #include <asm/cpufeature.h> #include <asm/cache.h> +#include <asm/global_data.h> #include <dm/uclass-internal.h> #include <linux/bitops.h> #include <linux/log2.h> @@ -746,3 +747,8 @@ __weak int cleanup_before_linux(void) return 0; } + +void arch_setup_gd(gd_t *new_gd) +{ + set_gd(new_gd); +} |