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| author | Tom Rini <trini@konsulko.com> | 2018-11-26 13:45:29 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-11-26 15:52:39 -0500 |
| commit | ef0b75d3d8afccebd3b9822de6bcae358d4bc0e3 (patch) | |
| tree | 9a1e0c04a8a3ecd641f0e219991eaf6ce98eefed /arch/riscv/include/asm/cache.h | |
| parent | 6b21502229035779059493b2193fd790448fe85e (diff) | |
| parent | 52923c6db7f00e0197ec894c8c1bb8a7681974bb (diff) | |
Merge git://git.denx.de/u-boot-riscv
Diffstat (limited to 'arch/riscv/include/asm/cache.h')
| -rw-r--r-- | arch/riscv/include/asm/cache.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ca83dd67c2f..ec8fe201d3c 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,6 +7,9 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +/* cache */ +void cache_flush(void); + /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. * We use that value for aligning DMA buffers unless the board config has |