diff options
| author | Rick Chen <rick@andestech.com> | 2018-02-12 11:07:58 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-03-30 13:13:22 +0800 |
| commit | bc0818a6a94429f2abd070afaa489266e78bf86b (patch) | |
| tree | 57c3ffdabe89dcabf8b95e8f711b43febebcb3d2 /arch/riscv/include/asm/encoding.h | |
| parent | 81cf7c8d45935a295991fe2cd1df286f0f47511f (diff) | |
riscv: checkpatch: Fix Macro argument reuse
It is CHECK reported by checkpatch.pl
CHECK: Macro argument reuse 'PTE' - possible side-effects?
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Diffstat (limited to 'arch/riscv/include/asm/encoding.h')
| -rw-r--r-- | arch/riscv/include/asm/encoding.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 5ff6d591499..dbf8d45fb72 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -121,7 +121,9 @@ #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) -#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ +#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ + typeof(_PTE) (PTE) = (_PTE); \ + typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) @@ -151,27 +153,31 @@ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) -#define write_csr(reg, val) ({ \ +#define write_csr(reg, _val) ({ \ +typeof(_val) (val) = (_val); \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ else \ asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) -#define swap_csr(reg, val) ({ unsigned long __tmp; \ +#define swap_csr(reg, _val) ({ unsigned long __tmp; \ +typeof(_val) (val) = (_val); \ if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ else \ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ __tmp; }) -#define set_csr(reg, bit) ({ unsigned long __tmp; \ +#define set_csr(reg, _bit) ({ unsigned long __tmp; \ +typeof(_bit) (bit) = (_bit); \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ __tmp; }) -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ +#define clear_csr(reg, _bit) ({ unsigned long __tmp; \ +typeof(_bit) (bit) = (_bit); \ if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ else \ |