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authorBin Meng <bmeng@tinylab.org>2023-06-21 23:11:46 +0800
committerLeo Yu-Chi Liang <ycliang@andestech.com>2023-07-12 13:21:40 +0800
commit9675d9202780fd996c00ad34f0360c89376205b3 (patch)
tree45a6e78f33e00d2a1bbe996d5895162c7f9dbf05 /arch/riscv/include/asm/global_data.h
parent7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 (diff)
riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/include/asm/global_data.h')
-rw-r--r--arch/riscv/include/asm/global_data.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 31ba72693d7..9d97517e124 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,8 +18,8 @@
struct arch_global_data {
long boot_hart; /* boot hart id */
phys_addr_t firmware_fdt_addr;
-#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
- void __iomem *clint; /* clint base address */
+#if CONFIG_IS_ENABLED(RISCV_ACLINT)
+ void __iomem *aclint; /* aclint base address */
#endif
#ifdef CONFIG_ANDES_PLICSW
void __iomem *plicsw; /* andes plicsw base address */