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| author | Tom Rini <trini@konsulko.com> | 2023-04-22 18:31:46 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-04-22 18:31:46 -0400 |
| commit | 802132c48a2e6b66ec83b7bb66fb96f2ba87c957 (patch) | |
| tree | 7462ddef96ed8310d888533f8d4d07a73e58a1fe /arch/riscv/include/asm/io.h | |
| parent | da142d1ec9fdc5d0e8641224ed245fcaa3cb55d8 (diff) | |
| parent | 04d16be55404ee07134b4171dea37eff9ad8fa5a (diff) | |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
* Add StarFive VisionFive v2 Board support
* Support CONFIG_REMAKE_ELF
* Code cleanups for RISC-V architecture
Diffstat (limited to 'arch/riscv/include/asm/io.h')
| -rw-r--r-- | arch/riscv/include/asm/io.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 220266e76f8..b16e6dfa376 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -180,7 +180,7 @@ static inline u64 readq(const volatile void __iomem *addr) * IO port access primitives * ------------------------- * - * The NDS32 doesn't have special IO access instructions just like ARM; + * The RISC-V doesn't have special IO access instructions just like ARM; * all IO is memory mapped. * Note that these are defined to perform little endian accesses * only. Their primary purpose is to access PCI and ISA peripherals. |