diff options
| author | Bin Meng <bmeng@tinylab.org> | 2023-06-21 23:11:46 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-12 13:21:40 +0800 |
| commit | 9675d9202780fd996c00ad34f0360c89376205b3 (patch) | |
| tree | 45a6e78f33e00d2a1bbe996d5895162c7f9dbf05 /arch/riscv/include/asm/syscon.h | |
| parent | 7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 (diff) | |
riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/include/asm/syscon.h')
| -rw-r--r-- | arch/riscv/include/asm/syscon.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h index f2b37975f37..5787702e746 100644 --- a/arch/riscv/include/asm/syscon.h +++ b/arch/riscv/include/asm/syscon.h @@ -12,7 +12,7 @@ */ enum { RISCV_NONE, - RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */ + RISCV_SYSCON_ACLINT, /* Advanced Core Local Interruptor (ACLINT) */ RISCV_SYSCON_PLICSW, /* Andes PLICSW */ }; |