diff options
author | Bin Meng <bmeng@tinylab.org> | 2023-06-21 23:11:46 +0800 |
---|---|---|
committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-12 13:21:40 +0800 |
commit | 9675d9202780fd996c00ad34f0360c89376205b3 (patch) | |
tree | 45a6e78f33e00d2a1bbe996d5895162c7f9dbf05 /arch/riscv/lib/aclint_ipi.c | |
parent | 7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 (diff) |
riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib/aclint_ipi.c')
-rw-r--r-- | arch/riscv/lib/aclint_ipi.c | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c new file mode 100644 index 00000000000..90b8e128cb1 --- /dev/null +++ b/arch/riscv/lib/aclint_ipi.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + * + * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). + * The CLINT block holds memory-mapped control and status registers + * associated with software and timer interrupts. + */ + +#include <common.h> +#include <dm.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/smp.h> +#include <asm/syscon.h> +#include <linux/err.h> + +/* MSIP registers */ +#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) + +DECLARE_GLOBAL_DATA_PTR; + +int riscv_init_ipi(void) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_driver(UCLASS_TIMER, + DM_DRIVER_GET(riscv_aclint_timer), &dev); + if (ret) + return ret; + + if (dev_get_driver_data(dev) != 0) + gd->arch.aclint = dev_read_addr_ptr(dev); + else + gd->arch.aclint = syscon_get_first_range(RISCV_SYSCON_ACLINT); + + if (!gd->arch.aclint) + return -EINVAL; + + return 0; +} + +int riscv_send_ipi(int hart) +{ + writel(1, (void __iomem *)MSIP_REG(gd->arch.aclint, hart)); + + return 0; +} + +int riscv_clear_ipi(int hart) +{ + writel(0, (void __iomem *)MSIP_REG(gd->arch.aclint, hart)); + + return 0; +} + +int riscv_get_ipi(int hart, int *pending) +{ + *pending = readl((void __iomem *)MSIP_REG(gd->arch.aclint, hart)); + + return 0; +} + +static const struct udevice_id riscv_aclint_swi_ids[] = { + { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_ACLINT }, + { } +}; + +U_BOOT_DRIVER(riscv_aclint_swi) = { + .name = "riscv_aclint_swi", + .id = UCLASS_SYSCON, + .of_match = riscv_aclint_swi_ids, + .flags = DM_FLAG_PRE_RELOC, +}; |