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| author | Tom Rini <trini@konsulko.com> | 2023-11-02 09:30:34 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-11-02 09:30:34 -0400 |
| commit | b0c391ce0c01064a96711965e22f5d745e73edc3 (patch) | |
| tree | fd9655433e4af8ee818e80267ff42713ff8d2290 /arch/riscv/lib/cache.c | |
| parent | 658caf0bf14e163be78b6fc063d883d1252163a2 (diff) | |
| parent | 9d22d4a7cef7f2fdaf5c060b71574e6f82ea5ff0 (diff) | |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ CI: Use OpenSBI 1.3.1 release for testing
+ riscv: Support resume after exception
+ rng: Support RNG provided by RISC-V Zkr ISA extension
+ board: starfive VF2: Support jtag
+ board: starfive VF2: Support TRNG driver
+ board: sifive unmatched: Move kernel load address
Diffstat (limited to 'arch/riscv/lib/cache.c')
| -rw-r--r-- | arch/riscv/lib/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index c46b49eb0ac..afad7e117f3 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end) { } -void invalidate_icache_range(unsigned long start, unsigned long end) +__weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the |