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| author | Bin Meng <bmeng.cn@gmail.com> | 2018-12-12 06:12:42 -0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2018-12-18 09:56:27 +0800 |
| commit | 496262cca63f25408c6715b39cea1747e8ce9b59 (patch) | |
| tree | c8484b9d177173fa3220163ccace7c0ecb8203c3 /arch/riscv/lib/interrupts.c | |
| parent | 4b3f5ed5ac1a4376c29c3010d25049c03de4ed57 (diff) | |
riscv: Fix context restore before returning from trap handler
sp cannot be loaded before restoring other registers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/lib/interrupts.c')
0 files changed, 0 insertions, 0 deletions