diff options
author | Kautuk Consul <kconsul@ventanamicro.com> | 2022-12-07 17:12:35 +0530 |
---|---|---|
committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-12-08 15:15:58 +0800 |
commit | ae3527f088062dc4e117b0c4d4319e068f5e44cd (patch) | |
tree | fa08dd5ee80ff563cb71240bafd1ad0b23ff22cd /arch/riscv/lib/interrupts.c | |
parent | 1c03ab9f4bdf19d1ac7afc157788bd0102ccd969 (diff) |
arch/riscv: add semihosting support for RISC-V
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/lib/interrupts.c')
-rw-r--r-- | arch/riscv/lib/interrupts.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 100be2e9662..e966afa7e3e 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -9,6 +9,7 @@ * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> */ +#include <linux/compat.h> #include <common.h> #include <efi_loader.h> #include <hang.h> @@ -17,6 +18,7 @@ #include <asm/ptrace.h> #include <asm/system.h> #include <asm/encoding.h> +#include <semihosting.h> DECLARE_GLOBAL_DATA_PTR; @@ -149,6 +151,29 @@ ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs) /* An UEFI application may have changed gd. Restore U-Boot's gd. */ efi_restore_gd(); + if (cause == CAUSE_BREAKPOINT && + CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) { + ulong pre_addr = epc - 4, post_addr = epc + 4; + + /* Check for prior and post addresses to be in same page. */ + if ((pre_addr & ~(PAGE_SIZE - 1)) == + (post_addr & ~(PAGE_SIZE - 1))) { + u32 pre = *(u32 *)pre_addr; + u32 post = *(u32 *)post_addr; + + /* Check for semihosting, i.e.: + * slli zero,zero,0x1f + * ebreak + * srai zero,zero,0x7 + */ + if (pre == 0x01f01013 && post == 0x40705013) { + disable_semihosting(); + epc += 4; + return epc; + } + } + } + is_irq = (cause & MCAUSE_INT); irq = (cause & ~MCAUSE_INT); |