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authorTom Rini <trini@konsulko.com>2022-12-08 08:28:14 -0500
committerTom Rini <trini@konsulko.com>2022-12-08 08:28:14 -0500
commit90609198223e9a3e4cf63e4225d3f9a3118171c9 (patch)
treeeb5d1aedd895f082736a27d81f59a74281a87026 /arch/riscv/lib/semihosting.c
parent341ba8d94b1c2f98766ad27b4a5b79ecafd2ba47 (diff)
parent57b9900cd59ad492f74390515901788459f1e8aa (diff)
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Kautuk's semihosting patch: move semihosting library from arm directory to common place and add RISC-V support - Zong's Kconfig patch: use "imply" instead of "select" to allow user to decide if SPL_SEPARATE_BSS should be selected
Diffstat (limited to 'arch/riscv/lib/semihosting.c')
-rw-r--r--arch/riscv/lib/semihosting.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/riscv/lib/semihosting.c b/arch/riscv/lib/semihosting.c
new file mode 100644
index 00000000000..d6593b02a6f
--- /dev/null
+++ b/arch/riscv/lib/semihosting.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Ventana Micro Systems Inc.
+ */
+
+#include <common.h>
+
+long smh_trap(int sysnum, void *addr)
+{
+ register int ret asm ("a0") = sysnum;
+ register void *param0 asm ("a1") = addr;
+
+ asm volatile (".align 4\n"
+ ".option push\n"
+ ".option norvc\n"
+
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 7\n"
+ ".option pop\n"
+ : "+r" (ret) : "r" (param0) : "memory");
+
+ return ret;
+}