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| author | Tom Rini <trini@konsulko.com> | 2020-07-02 09:53:34 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-02 09:53:34 -0400 |
| commit | 785195941b0746ac987a0ca501dae3e570b9f042 (patch) | |
| tree | 317f4d937fb80de27123a1d18adc29ad5bf9337c /arch/riscv/lib/sifive_clint.c | |
| parent | e2a4d24e6b1f3d30136e2dde7b6fbf35bd427b8a (diff) | |
| parent | add0dc1f7de91112d9e738f9482b09b75fa86acb (diff) | |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next
- Add Sipeed Maix support
- Update clock handler and proper cpu features
Diffstat (limited to 'arch/riscv/lib/sifive_clint.c')
| -rw-r--r-- | arch/riscv/lib/sifive_clint.c | 33 |
1 files changed, 11 insertions, 22 deletions
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index 5e0d25720bd..78fc6c868dd 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -24,22 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; -#define CLINT_BASE_GET(void) \ - do { \ - long *ret; \ - \ - if (!gd->arch.clint) { \ - ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \ - if (IS_ERR(ret)) \ - return PTR_ERR(ret); \ - gd->arch.clint = ret; \ - } \ - } while (0) - int riscv_get_time(u64 *time) { - CLINT_BASE_GET(); - *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); return 0; @@ -47,17 +33,24 @@ int riscv_get_time(u64 *time) int riscv_set_timecmp(int hart, u64 cmp) { - CLINT_BASE_GET(); - writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); return 0; } -int riscv_send_ipi(int hart) +int riscv_init_ipi(void) { - CLINT_BASE_GET(); + long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); + + if (IS_ERR(ret)) + return PTR_ERR(ret); + gd->arch.clint = ret; + + return 0; +} +int riscv_send_ipi(int hart) +{ writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); return 0; @@ -65,8 +58,6 @@ int riscv_send_ipi(int hart) int riscv_clear_ipi(int hart) { - CLINT_BASE_GET(); - writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); return 0; @@ -74,8 +65,6 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { - CLINT_BASE_GET(); - *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); return 0; |