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| author | Tom Rini <trini@konsulko.com> | 2023-06-22 09:59:43 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-06-22 09:59:43 -0400 |
| commit | eef4a771e85fc30a18719316a23d0ad1476ae1a5 (patch) | |
| tree | 723604929d4149b1e926fd6ecebc85ac4a513caf /arch/sandbox/cpu/cpu.c | |
| parent | 43dc016497ff9fd39139833852b0214f625fa4ca (diff) | |
| parent | 1c64b98c1ec40d2c9eb68af2d190e989dded8919 (diff) | |
Merge branch '2023-06-21-fix-get_ram_size-with-cache-enabled' into next
To quote the author:
Ensure that every write is flushed to memory and afterward reads are
from memory.
Since the algorithm rely on the fact that accessing to not existent
memory lead to write at addr / 2 without this modification accesses to
aliased (not physically present) addresses are cached and wrong size is
returned.
This was discovered while working on a TI AM625 based board where cache
is normally enabled, see commit c02712a74849 ("arm: mach-k3: Enable
dcache in SPL").
Diffstat (limited to 'arch/sandbox/cpu/cpu.c')
| -rw-r--r-- | arch/sandbox/cpu/cpu.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 51496338ad6..a1c5c7c4311 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -286,6 +286,11 @@ void sandbox_set_enable_pci_map(int enable) enable_pci_map = enable; } +int dcache_status(void) +{ + return 1; +} + void flush_dcache_range(unsigned long start, unsigned long stop) { } |