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authorDinesh Maniyam <dinesh.maniyam@intel.com>2025-07-28 14:19:42 +0800
committerTien Fong Chee <tien.fong.chee@intel.com>2025-07-30 17:45:31 +0800
commit4064e7c9fc42c1c376bd919a80b451273472f3df (patch)
tree37759faa1df8ae2444cd00e13175f1e02c0eff89 /arch/sandbox/lib/sandbox.c
parent169039f4f1df82cd4aeb95a9480b2bf5350c975c (diff)
socfpga_agilex5: config: Relocate malloc and bss address
With Inline ECC enabled, the bottom 1/8 of DDR is reserved for ECC parity bits and must not be used for general data address allocation. Previously, the SPL bss and malloc addresses were allocated inside this ECC parity region if the DDR size is 1GB. This caused ECC hardware to detect stale or invalid parity bits, leading to data correction attempts and DMA polling hangs or failures. Fix this by relocating the malloc and bss to the usable 7/8 region of DDR and is fully ECC-safe. This change ensures reliable ddr address operation and prevents unintended memory corruption. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'arch/sandbox/lib/sandbox.c')
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