diff options
| author | Tom Rini <trini@konsulko.com> | 2019-12-18 07:20:19 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-12-18 07:20:19 -0500 |
| commit | c0912f9bbfb26dd03d189953678691b799d35b6e (patch) | |
| tree | f879600cd26b8d4678a174854b623941e5dc2ada /arch/x86/cpu/ivybridge/sdram.c | |
| parent | 533c9f5714bdba79dc6f2629284d4c1a08a611d1 (diff) | |
| parent | a1d6dc3f84071f05574044f337dbdca70fae495d (diff) | |
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
Diffstat (limited to 'arch/x86/cpu/ivybridge/sdram.c')
| -rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 51ca4ad3017..cf34f94a91d 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -116,7 +116,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data) ret = read_seed_from_cmos(pei_data); if (ret) return ret; - ret = mrccache_get_region(NULL, &entry); + ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); if (ret) return ret; mrc_cache = mrccache_find_current(&entry); @@ -538,12 +538,14 @@ int dram_init(void) /* S3 resume: don't save scrambler seed or MRC data */ if (pei_data->boot_mode != PEI_BOOT_RESUME) { + struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; + /* * This will be copied to SDRAM in reserve_arch(), then written * to SPI flash in mrccache_save() */ - gd->arch.mrc_output = (char *)pei_data->mrc_output; - gd->arch.mrc_output_len = pei_data->mrc_output_len; + mrc->buf = (char *)pei_data->mrc_output; + mrc->len = pei_data->mrc_output_len; ret = write_seeds_to_cmos(pei_data); if (ret) debug("Failed to write seeds to CMOS: %d\n", ret); |