Merge branch 'next'

Bring in the following merges:

commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87
Merge: 87f69f467a83 63618e71e89b
Author: Tom Rini <trini@konsulko.com>
Date:   Fri Jan 3 09:48:47 2020 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next

    - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support

commit 87f69f467a8335b171c71bf217d2625d515acd7c
Merge: c0912f9bbfb2 4466b9970319
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 24 08:18:19 2019 -0500

    Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next

    - Enable DM driver on ppc/km boards
    - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
      T104x, P4080, P2041, P2020, P1020, P3041
    - Some updates in mpc85xx-ddr driver, km boards

commit c0912f9bbfb26dd03d189953678691b799d35b6e
Merge: 533c9f5714bd a1d6dc3f8407
Author: Tom Rini <trini@konsulko.com>
Date:   Wed Dec 18 07:20:19 2019 -0500

    Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

    - Various x86 common codes updated for TPL/SPL
    - I2C designware driver updated for PCI
    - ICH SPI driver updated to support Apollo Lake
    - Add Intel FSP2 base support
    - Intel Apollo Lake platform specific drivers support
    - Add a new board Google Chromebook Coral

commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1
Merge: 553cb0688782 033e18b47bd0
Author: Tom Rini <trini@konsulko.com>
Date:   Tue Dec 17 07:53:08 2019 -0500

    Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

    i2c: for next
    - misc: i2c_eeprom:
      Add partition support and add ability to query size
      of eeprom device and partitions
    - i2c common:
      add support for offset overflow in to address and add
      sandbox tests for it.

commit 553cb06887825314e74a9bdac337467c77d1db88
Merge: f39abbbc531e b4f98b3b16ec
Author: Tom Rini <trini@konsulko.com>
Date:   Thu Dec 12 08:18:59 2019 -0500

    Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next

    buildman improvements including toolchain environment feature
    sandbox unicode support in serial

1 files changed, 131 insertions, 0 deletions

diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
new file mode 100644
index 00000000000..226c7e66b3f
--- /dev/null
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <vbe.h>
+#include <video.h>
+#include <asm/fsp/fsp_support.h>
+#include <asm/mtrr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pixel {
+	u8 pos;
+	u8 size;
+};
+
+static const struct fsp_framebuffer {
+	struct pixel red;
+	struct pixel green;
+	struct pixel blue;
+	struct pixel rsvd;
+} fsp_framebuffer_format_map[] = {
+	[pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
+	[pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
+};
+
+static int save_vesa_mode(struct vesa_mode_info *vesa)
+{
+	const struct hob_graphics_info *ginfo;
+	const struct fsp_framebuffer *fbinfo;
+
+	ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
+
+	/*
+	 * If there is no graphics info structure, bail out and keep
+	 * running on the serial console.
+	 *
+	 * Note: on some platforms (eg: Braswell), the FSP will not produce
+	 * the graphics info HOB unless you plug some cables to the display
+	 * interface (eg: HDMI) on the board.
+	 */
+	if (!ginfo) {
+		debug("FSP graphics hand-off block not found\n");
+		return -ENXIO;
+	}
+
+	vesa->x_resolution = ginfo->width;
+	vesa->y_resolution = ginfo->height;
+	vesa->bits_per_pixel = 32;
+	vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
+	vesa->phys_base_ptr = ginfo->fb_base;
+
+	if (ginfo->pixel_format >= pixel_bitmask) {
+		debug("FSP set unknown framebuffer format: %d\n",
+		      ginfo->pixel_format);
+		return -EINVAL;
+	}
+	fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
+	vesa->red_mask_size = fbinfo->red.size;
+	vesa->red_mask_pos = fbinfo->red.pos;
+	vesa->green_mask_size = fbinfo->green.size;
+	vesa->green_mask_pos = fbinfo->green.pos;
+	vesa->blue_mask_size = fbinfo->blue.size;
+	vesa->blue_mask_pos = fbinfo->blue.pos;
+	vesa->reserved_mask_size = fbinfo->rsvd.size;
+	vesa->reserved_mask_pos = fbinfo->rsvd.pos;
+
+	return 0;
+}
+
+static int fsp_video_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct vesa_mode_info *vesa = &mode_info.vesa;
+	int ret;
+
+	printf("Video: ");
+
+	/* Initialize vesa_mode_info structure */
+	ret = save_vesa_mode(vesa);
+	if (ret)
+		goto err;
+
+	/*
+	 * The framebuffer base address in the FSP graphics info HOB reflects
+	 * the value assigned by the FSP. After PCI enumeration the framebuffer
+	 * base address may be relocated. Let's get the updated one from device.
+	 *
+	 * For IGD, it seems to be always on BAR2.
+	 */
+	vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
+
+	ret = vbe_setup_video_priv(vesa, uc_priv, plat);
+	if (ret)
+		goto err;
+
+	mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
+	mtrr_commit(true);
+
+	printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
+	       vesa->bits_per_pixel);
+
+	return 0;
+
+err:
+	printf("No video mode configured in FSP!\n");
+	return ret;
+}
+
+static const struct udevice_id fsp_video_ids[] = {
+	{ .compatible = "fsp-fb" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsp_video) = {
+	.name	= "fsp_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = fsp_video_ids,
+	.probe	= fsp_video_probe,
+};
+
+static struct pci_device_id fsp_video_supported[] = {
+	{ PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
+	{ },
+};
+
+U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);