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| author | Tom Rini <trini@konsulko.com> | 2025-04-16 16:52:28 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-04-17 07:51:37 -0600 |
| commit | 0f7a4ac96b27fa77b798c6c9598e05cf1654920b (patch) | |
| tree | 4b48ea8277232039a0475fa674b9cc951d15c80d /arch | |
| parent | c9c8df2c377e512553f2e9ad5d19c4b85efbf07d (diff) | |
| parent | d74728d8ed28fddc7ada266a9ece2cb858420cde (diff) | |
Merge patch series "airoha: add support spi/mmc/ethernet"
Christian Marangi <ansuelsmth@gmail.com> says:
This is continuation of the initial patchset for airoha
support.
Some are trivial fix for spi.
A new concept to setup SPI from detected NAND.
Sadly DTS node still need to be merged upstream so we
are currently adding them to u-boot dtsi and it's planned
to be dropped once they are accepted in upstream kernel.
Link: https://lore.kernel.org/r/20250407200208.25594-1-ansuelsmth@gmail.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/an7581-u-boot.dtsi | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi index 0316b73f3a5..a9297ca6503 100644 --- a/arch/arm/dts/an7581-u-boot.dtsi +++ b/arch/arm/dts/an7581-u-boot.dtsi @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/reset/airoha,en7581-reset.h> + / { reserved-memory { #address-cells = <2>; @@ -11,6 +13,94 @@ reg = <0x0 0x80000000 0x0 0x40000>; }; }; + + clk25m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clkxtal"; + }; + + vmmc_3v3: regulator-vmmc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + soc { + chip_scu: syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + + eth: ethernet@1fb50000 { + compatible = "airoha,en7581-eth"; + reg = <0 0x1fb50000 0 0x2600>, + <0 0x1fb54000 0 0x2000>, + <0 0x1fb56000 0 0x2000>; + reg-names = "fe", "qdma0", "qdma1"; + + resets = <&scuclk EN7581_FE_RST>, + <&scuclk EN7581_FE_PDMA_RST>, + <&scuclk EN7581_FE_QDMA_RST>, + <&scuclk EN7581_DUAL_HSI0_MAC_RST>, + <&scuclk EN7581_DUAL_HSI1_MAC_RST>, + <&scuclk EN7581_HSI_MAC_RST>, + <&scuclk EN7581_XFP_MAC_RST>; + reset-names = "fe", "pdma", "qdma", + "hsi0-mac", "hsi1-mac", "hsi-mac", + "xfp-mac"; + }; + + switch: switch@1fb58000 { + compatible = "airoha,en7581-switch"; + reg = <0 0x1fb58000 0 0x8000>; + }; + + snfi: spi@1fa10000 { + compatible = "airoha,en7581-snand"; + reg = <0x0 0x1fa10000 0x0 0x140>, + <0x0 0x1fa11000 0x0 0x600>; + + clocks = <&scuclk EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <2>; + }; + }; + + mmc0: mmc@1fa0e000 { + compatible = "mediatek,mt7622-mmc"; + reg = <0x0 0x1fa0e000 0x0 0x1000>, + <0x0 0x1fa0c000 0x0 0x60>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>; + clock-names = "source", "hclk"; + bus-width = <4>; + max-frequency = <52000000>; + vmmc-supply = <&vmmc_3v3>; + disable-wp; + cap-mmc-highspeed; + non-removable; + + assigned-clocks = <&scuclk EN7581_CLK_EMMC>; + assigned-clock-rates = <200000000>; + }; + }; +}; + +&scuclk { + compatible = "airoha,en7581-scu", "syscon"; }; &uart1 { |