diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-04-18 09:12:03 +0300 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-08-01 08:44:28 +0300 |
| commit | aa291c5f8bfbb761c2f2c84a501cf6eb4b655b2e (patch) | |
| tree | 7e14031766150aa749f8688e52d697d0e9c36f6b /arch | |
| parent | d564f395bcf933d5986723b4a02783338114977c (diff) | |
video: tegra: parametrize PCLK and DE polarity
Configure pixel clock and data enable polarity according to panel flags.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/dc.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index ab12cc9c7d0..22f8f977cc6 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -448,6 +448,9 @@ enum win_color_depth_id { #define LVS_OUTPUT_POLARITY_LOW BIT(28) #define LSC0_OUTPUT_POLARITY_LOW BIT(24) +/* DC_COM_PIN_OUTPUT_POLARITY3 0x309 */ +#define LSPI_OUTPUT_POLARITY_LOW BIT(8) + /* DC_COM_PIN_OUTPUT_SELECT6 0x31a */ #define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */ |