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| author | Simon Glass <sjg@chromium.org> | 2023-09-19 21:00:07 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-09-22 06:03:46 +0800 |
| commit | b1350636e69d4aac1e00aee5a327b5724f074420 (patch) | |
| tree | 7798b7d37cc280700f40ffd4464ac176f67f62ab /arch | |
| parent | 0c45c76ced7222ad8e5fb41b8be4d5237fd791a0 (diff) | |
x86: coreboot: Look for DBG2 UART in SPL too
If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
0 files changed, 0 insertions, 0 deletions