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authorTom Rini <trini@konsulko.com>2023-10-05 13:26:44 -0400
committerTom Rini <trini@konsulko.com>2023-10-05 13:26:44 -0400
commitbe2abe73df58a35da9e8d5afb13fccdf1b0faa8e (patch)
treea41b676d6169cd846d33dcf18c8e8c6ea181784c /arch
parentcb59d23584a7a0f2431025a56f4938d424c49ca5 (diff)
parent7cfdacbe8020292845bd5eba63b576b8586c433c (diff)
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
+ ae350: modify memory layout and target name + ae350: use generic RISC-V timer driver in S-mode + Support bootstage report for RISC-V + Support C extension exception command for RISC-V + Add Starfive timer support
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/Kconfig5
-rw-r--r--arch/riscv/cpu/andesv5/Kconfig3
-rw-r--r--arch/riscv/dts/Makefile2
-rw-r--r--arch/riscv/lib/bootm.c2
4 files changed, 7 insertions, 5 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 1c62c2345b0..183885ebe7d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
prompt "Target select"
optional
-config TARGET_AE350
- bool "Support ae350"
+config TARGET_ANDES_AE350
+ bool "Support Andes ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
@@ -141,6 +141,7 @@ config RISCV_MMODE
config RISCV_SMODE
bool "Supervisor"
+ imply DEBUG_UART
help
Choose this option to build U-Boot for RISC-V S-Mode.
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
index 82bb5a2a532..f311291aedb 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andesv5/Kconfig
@@ -4,8 +4,9 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply ANDES_PLMT_TIMER
+ imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply V5L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f1525cb6680..be6c8a42272 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 276677a5e2f..cc30efc9049 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -42,7 +42,7 @@ static void announce_and_cleanup(int fake)
#ifdef CONFIG_BOOTSTAGE_FDT
bootstage_fdt_add_report();
#endif
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
bootstage_report();
#endif