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authorAlif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>2025-08-03 18:24:44 -0700
committerTien Fong Chee <tien.fong.chee@intel.com>2025-08-08 22:20:50 +0800
commitc8f5166cff0ccdb1966ed786dba88e9548ce632e (patch)
tree51a7980a4ce504306ad5af9e2f166fa0813ab688 /arch
parent3a1cd4ffd7483465bf24539e9ba94f92dd17cd5d (diff)
sysreset: socfpga: soc64: Enable L2 reset
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes the magic word into system manager's scratch register to indicate the system has performed L2 reset and request reset manager to perform hardware handshake and then trigger L2 reset. CPU0 put itself into WFI mode. L2 reset will reboot all HPS CPU cores after which all HPS cores are in WFI mode. L2 reset is followed by warm reset request by SPL via RMR_EL3 system register. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4e7593616d8..af81d937201 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1173,7 +1173,7 @@ config ARCH_SOCFPGA
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
- TARGET_SOCFPGA_SOC64
+ TARGET_SOCFPGA_SOC64
select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
imply CMD_DM
imply CMD_MTDPARTS