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| author | Heiko Thiery <heiko.thiery@gmail.com> | 2025-06-12 13:50:15 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-06-26 15:54:18 -0600 |
| commit | cf2abe7b1e6d5a2266d14f801d4eb52edec39ed6 (patch) | |
| tree | 2d2f4168f796d53f9a0a841455e3923329b4c688 /arch | |
| parent | 5609f200d062a25c1b3baac94a78e3eef0a3cd75 (diff) | |
mach-k3: j722s: enable caches for the SPL stage
This is same as done in commit 27cd65ca1bf1 ("mach-k3: am62ax: enable
caches for the SPL stage").
This is resulting in ~2x speedup in the A53 SPL stage.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-k3/j722s/j722s_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c index d8123f282ee..1180c75f551 100644 --- a/arch/arm/mach-k3/j722s/j722s_init.c +++ b/arch/arm/mach-k3/j722s/j722s_init.c @@ -166,6 +166,8 @@ static void k3_mem_init(void) if (ret) panic("DRAM init failed: %d\n", ret); } + + spl_enable_cache(); } static __maybe_unused void enable_mcu_esm_reset(void) |