global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

11 files changed, 105 insertions, 105 deletions

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d530e0655bc..d09c21d5d9b 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -168,18 +168,18 @@ static void mmu_setup(void)
 	/* Level 1 has 512 entries */
 	for (i = 0; i < 512; i++) {
 		/* Mapping for PCIe 1 */
-		if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
-		    va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
-				 CONFIG_SYS_PCIE_MMAP_SIZE))
+		if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
+		    va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
+				 CFG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+				      CFG_SYS_PCIE1_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		/* Mapping for PCIe 2 */
-		else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
-			 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
-				     CONFIG_SYS_PCIE_MMAP_SIZE))
+		else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
+			 va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
+				     CFG_SYS_PCIE_MMAP_SIZE))
 			set_pgsection(level1_table, i,
-				      CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+				      CFG_SYS_PCIE2_PHYS_BASE + va_start,
 				      MT_DEVICE_MEM);
 		else
 			set_pgsection(level1_table, i,
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c11341a1d38..ef71e2cf2bc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -257,26 +257,26 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	  CFG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	  CFG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	  CFG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-	{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-	  CONFIG_SYS_PCIE4_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+	{ CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
+	  CFG_SYS_PCIE4_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -368,19 +368,19 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-	  CONFIG_SYS_PCIE1_PHYS_SIZE,
+	{ CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+	  CFG_SYS_PCIE1_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-	  CONFIG_SYS_PCIE2_PHYS_SIZE,
+	{ CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+	  CFG_SYS_PCIE2_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-	{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-	  CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+	{ CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+	  CFG_SYS_PCIE3_PHYS_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
@@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void)
 	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
-			case CONFIG_SYS_PCIE1_PHYS_ADDR:
+			case CFG_SYS_PCIE1_PHYS_ADDR:
 				final_map[i].phys = 0x2000000000ULL;
 				final_map[i].virt = 0x2000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-			case CONFIG_SYS_PCIE2_PHYS_ADDR:
+			case CFG_SYS_PCIE2_PHYS_ADDR:
 				final_map[i].phys = 0x2800000000ULL;
 				final_map[i].virt = 0x2800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-			case CONFIG_SYS_PCIE3_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+			case CFG_SYS_PCIE3_PHYS_ADDR:
 				final_map[i].phys = 0x3000000000ULL;
 				final_map[i].virt = 0x3000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-			case CONFIG_SYS_PCIE4_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+			case CFG_SYS_PCIE4_PHYS_ADDR:
 				final_map[i].phys = 0x3800000000ULL;
 				final_map[i].virt = 0x3800000000ULL;
 				final_map[i].size = 0x800000000ULL;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4db479140ea..20f96713871 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -35,17 +35,17 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x200000000
+#define CFG_SYS_PCIE4_PHYS_SIZE	0x200000000
 #else
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
-#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#ifndef CFG_SYS_PCIE3_PHYS_SIZE
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
 #endif
-#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE4_PHYS_SIZE	0x800000000
 #define SYS_PCIE5_PHYS_SIZE		0x800000000
 #define SYS_PCIE6_PHYS_SIZE		0x800000000
 #endif
@@ -83,9 +83,9 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
 #define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
-#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CFG_SYS_PCIE3_PHYS_SIZE	0x800000000
 #define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
 #define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 85ac5eb2813..64dc7c88b7f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -33,8 +33,8 @@
 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
 #define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
 #define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
@@ -90,9 +90,9 @@
 #define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
 #define QMAN_CQSIDR_REG				0x20a80
 
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
 #ifdef CONFIG_ARCH_LS1012A
 #define PCIE_LUT_BASE				0xC0000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 59488a04e40..cd112402e0c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -192,35 +192,35 @@
 
 
 /* PCIe */
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR				(CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR				(CONFIG_SYS_IMMR + 0x2900000)
 #endif
 
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x9800000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
+#define CFG_SYS_PCIE4_PHYS_ADDR		0x9800000000ULL
 #define SYS_PCIE5_PHYS_ADDR			0xa000000000ULL
 #define SYS_PCIE6_PHYS_ADDR			0xa800000000ULL
 #elif CONFIG_ARCH_LS1088A
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x2000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x2800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x3000000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x2000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x2800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x3000000000ULL
 #elif CONFIG_ARCH_LS1028A
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x01f0000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x01f0000000ULL
 /* this is used by integrated PCI on LS1028, includes ECAM and register space */
-#define CONFIG_SYS_PCIE3_PHYS_SIZE		0x0010000000ULL
+#define CFG_SYS_PCIE3_PHYS_SIZE		0x0010000000ULL
 #else
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
+#define CFG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
 #endif
 
 /* Device Configuration */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 033341dbfb6..62026bda9e2 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -55,22 +55,22 @@
 
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
-
-#define CONFIG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
-#define CONFIG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
-#define CONFIG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
-#define CONFIG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
+#define CFG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+
+#define CFG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
+#define CFG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
+#define CFG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
+#define CFG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
+#define CFG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
 /*
  * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
  * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
  */
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		(CONFIG_SYS_PCIE1_PHYS_BASE + \
-						 CONFIG_SYS_PCIE1_VIRT_ADDR)
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		(CONFIG_SYS_PCIE2_PHYS_BASE + \
-						 CONFIG_SYS_PCIE2_VIRT_ADDR)
+#define CFG_SYS_PCIE1_PHYS_ADDR		(CFG_SYS_PCIE1_PHYS_BASE + \
+						 CFG_SYS_PCIE1_VIRT_ADDR)
+#define CFG_SYS_PCIE2_PHYS_ADDR		(CFG_SYS_PCIE2_PHYS_BASE + \
+						 CFG_SYS_PCIE2_VIRT_ADDR)
 
 /* SATA */
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index ead62cd0387..f2eb6fcb463 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -337,10 +337,10 @@
 #define CONFIG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0		(0x40000000)
-#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_BAR0		(0x40000000)
+#define CFG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CFG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
 #endif
 #endif				/* CONFIG_M547x */
 
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index d2b6b05bdaf..47ca74c5c35 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -24,13 +24,13 @@ static struct {
 	u32 size;
 } mpc83xx_pcie_cfg_space[] = {
 	{
-		.base = CONFIG_SYS_PCIE1_CFG_BASE,
-		.size = CONFIG_SYS_PCIE1_CFG_SIZE,
+		.base = CFG_SYS_PCIE1_CFG_BASE,
+		.size = CFG_SYS_PCIE1_CFG_SIZE,
 	},
-#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
+#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE)
 	{
-		.base = CONFIG_SYS_PCIE2_CFG_BASE,
-		.size = CONFIG_SYS_PCIE2_CFG_SIZE,
+		.base = CFG_SYS_PCIE2_CFG_BASE,
+		.size = CFG_SYS_PCIE2_CFG_SIZE,
 	},
 #endif
 };
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index abc14fae4ec..d5df02d39d8 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -387,7 +387,7 @@ void fdt_fixup_liodn(void *blob)
 	fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
 #endif
 
-	ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
+	ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR;
 	int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
 
 	if (pci_ver >= 0x0204) {
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 06f9bfb8ac7..809ab1d4187 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno);
 
 #define SET_STD_PCI_INFO(x, num) \
 {			\
-	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
-	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
-	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
-	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
-	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
-	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
-	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+	x.regs = CFG_SYS_PCI##num##_ADDR;	\
+	x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \
+	x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \
+	x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \
+	x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \
+	x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \
+	x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \
 	x.law = LAW_TRGT_IF_PCI_##num; \
 	x.pci_num = num; \
 }
 
 #define SET_STD_PCIE_INFO(x, num) \
 {			\
-	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
-	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
-	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
-	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
-	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
-	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
-	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+	x.regs = CFG_SYS_PCIE##num##_ADDR;	\
+	x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \
+	x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \
+	x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \
+	x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \
+	x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \
+	x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \
 	x.law = LAW_TRGT_IF_PCIE_##num; \
 	x.pci_num = num; \
 }
 
 #define __FT_FSL_PCI_SETUP(blob, compat, num) \
-	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+	ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR)
 
 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \
-	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+	ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR)
 
 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 78c0d054965..9ae698743ee 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2662,9 +2662,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_PAMU_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
 
-#define CONFIG_SYS_PCIE1_ADDR \
+#define CFG_SYS_PCIE1_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
-#define CONFIG_SYS_PCIE2_ADDR \
+#define CFG_SYS_PCIE2_ADDR \
 	(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
 
 #define CONFIG_SYS_SFP_ADDR  \