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| author | Tom Rini <trini@konsulko.com> | 2023-02-23 17:32:22 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-02-23 17:40:18 -0500 |
| commit | 0024e7f72b689f8c2df731a69e20f47b6f8dc5a7 (patch) | |
| tree | 03da9b68c29df4ffa5c181acca8ce6176636a410 /board/avionic-design/tec-ng/tec-ng-spl.c | |
| parent | 0b58258a33280a536c5b1e5e90dfdf0b5b5852cc (diff) | |
| parent | 5a8fe1ee818e0f8a74fa088f6a3d705a01b6afbe (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Diffstat (limited to 'board/avionic-design/tec-ng/tec-ng-spl.c')
| -rw-r--r-- | board/avionic-design/tec-ng/tec-ng-spl.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/board/avionic-design/tec-ng/tec-ng-spl.c b/board/avionic-design/tec-ng/tec-ng-spl.c new file mode 100644 index 00000000000..6e544641833 --- /dev/null +++ b/board/avionic-design/tec-ng/tec-ng-spl.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +/* I2C addr is in 8 bit */ +#define TPS65911_I2C_ADDR 0x5A +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, + TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} |